Trench-gate LDMOS structures

• US 8,198,677 B2
• Filed: 07/08/2009
• Issued: 06/12/2012
• Est. Priority Date: 10/03/2002
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Sapp, Steven, Wilson, Peter H.
• Primary Examiner(s): MATTHEWS, COLLEEN ANN
• Application Number:
  US12/499,778
• Publication Number:
  US 20090273026A1
• Time in Patent Office: 1,070 Days
• Field of Search: 257328-341, 257/E29.258, 257/E29.264, 257/E29.266, 257/E29.268
• US Class Current: 257/331
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

MOSFET devices for RF applications that use a trench-gate in place of the lateral gate conventionally used in lateral MOSFET devices. A trench-gate provides devices with a single, short channel for high frequency gain. Embodiments of the present invention provide devices with an asymmetric oxide in the trench gate, as well as LDD regions that lower the gate-drain capacitance for improved RF performance. Refinements to these TG-LDMOS devices include placing a source-shield conductor below the gate and placing two gates in a trench-gate region. These improve device high-frequency performance by decreasing gate-to-drain capacitance. Further refinements include adding a charge balance region to the LDD region and adding source-to-substrate or drain-to-substrate vias.

Claims

1. A field effect transistor comprising:

a first silicon region comprising a body region having a first conductivity type, the first silicon region having a top surface;

a gate-trench region extending from the top surface of the first silicon region into the first silicon region, wherein the gate-trench region has a first sidewall, a bottom, and a second sidewall, the gate-trench region having;

a first gate region including a conductive region; and

an insulating region separating the first gate region from the first sidewall, the bottom, and the second sidewall of the gate-trench region;

a highly-doped drain region of a second conductivity type at the top surface of the first silicon region and contacting a drain electrode, the highly-doped drain region being laterally spaced from the gate-trench region, the second conductivity type being opposite to the first conductivity type;

a lightly-doped drain region of the second conductivity type in the first silicon region, the lightly-doped drain region laterally extending along the top surface of the first silicon region between the second sidewall of the gate-trench region and the highly-doped drain region, and further extending under the bottom of the gate-trench region; and

wherein a portion of the lightly-doped drain region laterally extending along the top surface of the first silicon region extends to a depth shallower than a bottom of the gate-trench region.

2. The transistor of claim 1 further comprising a second gate region located between the top surface of the first silicon region and at least a portion of the first gate region.

3. The transistor of claim 2 wherein one of the first and second gate regions is coupled to a source region of the transistor.

4. The transistor of claim 1 further comprising a source region at the top surface of the first silicon region, the source region including a dopant region of the second conductivity type.

5. The transistor of claim 1 wherein the insulating region comprises:

a first insulating layer between the first gate region and the first sidewall; and

a second insulating layer between the first gate region and the second sidewall, the second insulating layer being thicker than the first insulating layer.

6. The transistor of claim 1 further comprising:

a charge-balance region of the first conductivity type, the charge-balance region being located in the lightly-doped drain region.

7. The transistor of claim 1 wherein:

the first silicon region comprises an epitaxial layer formed on a substrate; and

the transistor further comprises a source-substrate via coupling the source to the substrate.

8. The transistor of claim 1 wherein:

the first silicon region is an epitaxial layer formed on a substrate; and

the transistor further comprises a drain-substrate via coupling the source to the substrate.

9. A field effect transistor comprising:

a first silicon region comprising a body region having a first conductivity type, the first silicon region having a top surface;

a gate-trench region extending from the top surface of the first silicon region into the first silicon region, wherein the gate-trench region has a first sidewall, a bottom, and a second sidewall, the gate-trench region having;

a first gate region including a first conductive region;

a second gate region including a second conductive region, the second gate region located between the top surface of the first silicon region and at least a portion of the first gate region;

a first insulating layer between the second gate region and the first sidewall; and

a second insulating layer between the second gate region and the second sidewall, the second insulating layer being thicker than the first insulating layer;

a highly-doped drain region of a second conductivity type at the top surface of the first silicon region and contacting a drain electrode, the highly-doped drain region being laterally spaced from the gate-trench region, the second conductivity type being opposite to the first conductivity type;

a lightly-doped drain region of the second conductivity type in the first silicon region, the lightly-doped drain region laterally extending along the top surface of the first silicon region between the second sidewall of the gate-trench region and the highly-doped drain region, and further extending under the bottom of the gate-trench region; and

wherein a portion of the lightly-doped drain region laterally extending along the top surface of the first silicon region extends to a depth shallower than a bottom of the gate-trench region.

10. The transistor of claim 9 wherein one of the first and second gate regions is coupled to a source region of the transistor.

11. The transistor of claim 9 wherein the first gate region is coupled to a first gate electrode, and the second gate region is coupled to a second gate electrode.

12. The transistor of claim 9 further comprising a source region at the top surface of the first silicon region, the source region having a dopant region of the second conductivity type.

13. The transistor of claim 9 further comprising:

a charge-balance region of the first conductivity type, the charge-balance region being located in the lightly-doped drain region.

14. The transistor of claim 9 wherein:

the first silicon region comprises an epitaxial layer formed on a substrate; and

the transistor further comprises a source-substrate via coupling the source to the substrate.

15. The transistor of claim 9 wherein:

the first silicon region comprise an epitaxial layer formed on a substrate; and

the transistor further comprises a drain-substrate via coupling the source to the substrate.