Semiconductor wafer structure

• US 8,198,713 B2
• Filed: 07/13/2007
• Issued: 06/12/2012
• Est. Priority Date: 07/13/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Hufgard, Erich
• Primary Examiner(s): Tran, Minhloan T
• Assistant Examiner(s): HARRISTON, WILLIAM A
• Application Number:
  US11/777,743
• Publication Number:
  US 20090014857A1
• Time in Patent Office: 1,796 Days
• Field of Search: 257/777, 257/678
• US Class Current: 257/678
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06575 Auxiliary carrier between devices, the carrier having no electrical connection structure
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1433 Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding

Abstract

One embodiment provides a semiconductor wafer structure including a semiconductor wafer and a spacer layer. The semiconductor wafer includes active areas. The spacer layer is configured to provide spacing between the semiconductor dice in a stacked die package and the spacer layer is disposed on one side of the semiconductor wafer.

Claims

1. A semiconductor wafer structure, comprising:

a semiconductor wafer including active areas on a top side and having a back side that opposes the top side; and

a solid spacer layer configured to be singulated into spacers that provide spacing between semiconductor dice in stacked die packages, wherein the solid spacer layer is attached to and directly contacts the back side of the semiconductor wafer, and the solid spacer layer is patterned to include open areas configured to be situated over bond pads of semiconductor die from at least one other semiconductor wafer in the stacked die packages and patterned to include other open areas configured to be situated over at least one of an active element, a MEM system, a sensor, or a light emitting element of the semiconductor die from the at least one other semiconductor wafer in the stacked die packages, wherein the solid spacer layer includes different patterns corresponding to different full semiconductor die from the at least one other semiconductor wafer.

2. The semiconductor wafer structure of claim 1, wherein the solid spacer layer is attached to the semiconductor wafer via one of an adhesive, solder, and anodic bonding.

3. The semiconductor wafer structure of claim 1, wherein the solid spacer layer is patterned before being disposed on the back side of the semiconductor wafer.

4. The semiconductor wafer structure of claim 1, wherein the solid spacer layer is patterned via one of photolithographic processing and etching, and photoablation.

5. The semiconductor wafer structure of claim 1, wherein the solid spacer layer is patterned via a mechanical treatment.

6. The semiconductor wafer structure of claim 5, wherein the mechanical treatment includes one of sawing, milling, grinding, punching, molding, casting, and drilling.

7. A method of packaging semiconductor dice, comprising:

providing semiconductor dice in a semiconductor wafer;

disposing a pre-formed solid spacer layer on one side of the semiconductor wafer; and

thereafter

patterning the pre-formed solid spacer layer, wherein the patterning creates open areas in the pre-formed solid spacer layer and the open areas are situated over active areas defining a topology in semiconductor dice in packages.

8. The method of claim 7, wherein disposing a pre-formed solid spacer layer, comprises:

attaching the pre-formed solid spacer layer via one of an adhesive, solder, and anodic bonding.

9. The method of claim 7, comprising:

patterning the pre-formed solid spacer layer via one of photolithographic processing and etching, and photoablation.

10. The method of claim 7, comprising:

patterning the pre-formed solid spacer layer via a mechanical treatment.

11. The method of claim 7, comprising:

patterning the pre-formed solid spacer layer via one of sawing, milling, grinding, punching, molding, casting, and drilling.

16. The method of claim 7, wherein patterning the pre-formed solid spacer layer includes providing different patterns corresponding to different ones of the semiconductor dice.

12. A method of providing spacers in stacked die packages, comprising:

providing semiconductor dice in a semiconductor wafer including active areas;

attaching a pre-formed solid slab spacer layer to one side of the semiconductor wafer; and

thereafter

patterning the pre-formed solid slab spacer layer, wherein the patterning creates open areas in the pre-formed solid slab spacer layer and the open areas are situated over at least one of a bond pad, an active element, a MEM system, a sensor, or a light emitting element in semiconductor dice in the stacked die packages.

13. The method of claim 12, comprising:

singulating the pre-formed solid slab spacer layer into singulated spacers.

14. The method of claim 13, wherein the semiconductor dice are integrated circuits and comprising:

singulating the semiconductor wafer into singulated integrated circuit die.

15. The method of claim 12, wherein attaching a pre-formed solid slab spacer layer comprises:

attaching the pre-formed solid slab spacer layer to the back side of the semiconductor wafer.