TFT-LCD array substrate and method of manufacturing the same

• US 8,199,270 B2
• Filed: 12/29/2009
• Issued: 06/12/2012
• Est. Priority Date: 12/30/2008
• Status: Active Grant

• Current Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.)
• Inventors: Liu, Xiang, Rim, Seung Moo, Chen, Xu, Xie, Zhenyu
• Primary Examiner(s): Rude, Timothy L
• Application Number:
  US12/648,480
• Publication Number:
  US 20100165227A1
• Time in Patent Office: 896 Days
• Field of Search: 349/43
• US Class Current: 349/43
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

The present invention relates to a method of manufacturing an array substrate of TFT-LCD. The method includes the following steps. In step 1, a gate metal thin film is deposited on a substrate and patterned into gate electrodes and gate lines by a first patterning process. In step 2, a gate insulation layer, a semiconductor layer and a barrier layer are subsequently deposited on the resultant structure of step 1 and are patterned into gate insulation layer pattern, semiconductor layer pattern and barrier layer pattern by a second patterning process, wherein the barrier layer is used for preventing the semiconductor layer at the TFT channel from being etched. In step 3, an ohmic contact layer, a transparent conductive layer, a source drain metal layer and a passivation layer are subsequently deposited on the resultant structure of step 2, and are patterned into ohmic contact layer pattern, pixel electrodes, data lines, source electrodes, drain electrodes and passivation layer pattern in a patterning process.

Claims

1. An array substrate of thin film transistor liquid crystal display (TFT-LCD) comprising gate lines and data lines, in which pixel electrodes and thin film transistors are formed within the pixel region defined by the gate lines and the data lines, wherein a barrier layer pattern is disposed between a semiconductor layer pattern and an ohmic contact layer pattern in the thin film transistor for preventing the semiconductor layer pattern from being etched, wherein an area of the barrier layer pattern is smaller than an area of the semiconductor layer pattern so that the ohmic contact layer pattern is in contact with the semiconductor layer pattern.

2. The array substrate of TFT-LCD according to claim 1, wherein the semiconductor layer pattern is formed on the gate insulation layer, the ohmic contact layer pattern is formed on the gate insulation layer;

the semiconductor layer pattern and the barrier layer pattern, the pixel electrode is disposed on the ohmic contact layer pattern;

the drain electrode is disposed on the pixel electrode;

a TFT channel is formed between the source electrode and the drain electrode;

the source electrode is connected to the data line.

3. The array substrate of TFT-LCD according to claim 2, wherein the gate insulation layer, the semiconductor layer pattern and the barrier layer pattern are formed in a first patterning process;

the ohmic contact layer, the pixel electrode, the source electrode, the drain electrode, the TFT channel and the data line are patterned in a second patterning process; and

a passivation layer is disposed on the pixel electrode, the source electrode, the drain electrode, the TFT channel, the data line.

4. The array substrate of TFT-LCD according to claim 3, wherein the thickness of the barrier layer pattern is 100-300 nm.

5. The array substrate of TFT-LCD according to claim 2, wherein the gate insulation layer, the semiconductor layer and the barrier layer are formed in a first patterning process;

the ohmic contact layer, the pixel electrode and the data line are patterned in a second patterning process;

the source electrode, the drain electrode, the TFT channel and the passivation layer are patterned in a third patterning process; and

the passivation layer is disposed on the pixel electrode, the source electrode, the drain electrode and the data line.

6. The array substrate of TFT-LCD according to claim 5, wherein the thickness of the barrier layer pattern is 100-300 nm.

7. The array substrate of TFT-LCD according to claim 2, wherein the thickness of the barrier layer pattern is 100-300 nm.

8. The array substrate of TFT-LCD according to claim 7, wherein the thickness of the semiconductor layer pattern is 40-100 nm.

9. The array substrate of TFT-LCD according to claim 1, wherein the thickness of the barrier layer pattern is 100-300 nm.

10. The array substrate of TFT-LCD according to claim 9, wherein the thickness of the semiconductor layer pattern is 40-100 nm.