In plane switching mode liquid crystal display device and fabrication method thereof

• US 8,199,302 B2
• Filed: 03/08/2011
• Issued: 06/12/2012
• Est. Priority Date: 10/09/2003
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Hong, Hyung Ki
• Primary Examiner(s): CHIEN, LUCY P
• Application Number:
  US13/043,114
• Publication Number:
  US 20110157534A1
• Time in Patent Office: 462 Days
• Field of Search: None
• US Class Current: 349/141
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/136222 Colour filters incorporated in the active matrix substrate
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer

Abstract

An IPS mode LCD includes first and second substrates. A thin film transistor and a color filter layer are formed on the first substrate. A common electrode and a pixel electrode are arranged in a zigzag configuration on the first substrate. A liquid crystal layer is disposed between the first and second substrates.

Claims

1. An in-plane switching (IPS) mode liquid crystal display (LCD) comprising:

a first substrate and a second substrate;

a color filter layer on the first substrate;

a gate insulating layer on an entire region of the color filter layer;

a thin film transistor on the gate insulating layer;

a black matrix layer on at least the thin film transistor;

a passivation layer configured to contact the black matrix layer and the gate insulating layer;

a common electrode and a pixel electrode arranged in a zigzag configuration on the first substrate; and

a liquid crystal layer between the first and second substrates,

wherein the black matrix layer and the pixel electrode are spaced apart from each other on the first substrate.

2. The IPS mode LCD of claim 1, further comprising:

a gate line and a data line crossing with each other on the color filter layer and defining a pixel region, wherein the black matrix layer is disposed on the thin film transistor, the gate line and the data line.

3. The IPS mode LCD of claim 1, wherein the passivation layer covers upper and side surfaces of the black matrix.

4. The IPS mode LCD of claim 1, wherein the common electrode and the pixel electrode is disposed directly on the passivation layer.

5. The IPS mode LCD of claim 1, wherein the passivation layer is disposed in a pixel region laterally adjacent to the black matrix layer.

6. The IPS mode LCD of claim 2, wherein the black matrix layer is formed of black resin.

7. The IPS mode LCD of claim 1, further comprising an overcoat layer between the color filter layer and the thin film transistor.

8. The IPS mode LCD of claim 1, further comprising alignment films disposed on the first and second substrates.

9. The IPS mode LCD of claim 1, wherein the zigzag configuration has a bend angle less than 30°

with respect to an alignment direction of the liquid crystal layer.

10. The IPS mode LCD of claim 1, wherein the zigzag configuration has a bend angle range of 60-120°

, except 90°

, with respect to an alignment direction of the liquid crystal layer.

11. The IPS mode LCD of claim 1, wherein the common and pixel electrodes are formed of a transparent conductive material.

12. The IPS mode LCD of claim 4, further comprising a common line adjacent to the gate line and in parallel with the gate line,

wherein the common line is formed to extend from the common electrode, and

wherein the common line is disposed directly on the passivation layer.

13. The IPS mode LCD of claim 1, wherein a first upper portion of the passivation layer corresponding to the black matrix has the same plane surface as that of a second upper portion of the passivation layer corresponding to the gate insulating layer.

14. The IPS mode LCD of claim 1, wherein the black matrix layer is spaced apart from the color filter layer.