Apparatus for variable resistive memory punchthrough access method
First Claim
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1. An apparatus comprising:
- a plurality of bit lines and a plurality of source lines forming a cross-point array;
a memory unit adjacent to at least selected cross-points of the cross-point array, the memory unit comprising a variable resistive data cell;
a transistor electrically connected between the variable resistive data cell and one of the plurality of source lines, wherein a gate of the transistor is not electrically connected to a word line, source line or bit line and the transistor is configured to operate in punchthrough mode to write a data state to the memory unit.
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Abstract
Variable resistive punchthrough access methods are described. The methods include switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction. The write current is provided by a transistor being electrically coupled to the variable resistive data cell and a source line. The write current passes through the transistor in punchthrough mode.
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Citations
21 Claims
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1. An apparatus comprising:
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a plurality of bit lines and a plurality of source lines forming a cross-point array; a memory unit adjacent to at least selected cross-points of the cross-point array, the memory unit comprising a variable resistive data cell; a transistor electrically connected between the variable resistive data cell and one of the plurality of source lines, wherein a gate of the transistor is not electrically connected to a word line, source line or bit line and the transistor is configured to operate in punchthrough mode to write a data state to the memory unit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An apparatus comprising:
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a plurality of bit lines and a plurality of source lines forming a cross-point array; a memory unit adjacent to at least selected cross-points of the cross-point array, the memory unit comprising a variable resistive data cell; a transistor electrically connected between the variable resistive data cell and one of the plurality of source lines, wherein a gate of the transistor is a metal-oxide-semiconductor field effect transistor having a merged source depletion region and a drain depletion region. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. An apparatus comprising:
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a source line electrically connected to a plurality of variable resistive data cells; a plurality of bit lines, wherein each bit line is electrically connected to a variable resistive data cell; a plurality of transistors, each transistor is electrically connected between each variable resistive data cell and associated bit line, at least one transistor is a metal-oxide-semiconductor field effect transistor having a merged source depletion region and a drain depletion region. - View Dependent Claims (18, 19, 20, 21)
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Specification
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Current AssigneeSeagate Technology LLC (Seagate Technology Holdings Plc)
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Original AssigneeSeagate Technology LLC (Seagate Technology Holdings Plc)
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InventorsKhoury, Maroun Georges, Liu, Hongyue, Lee, Brian, Carter, Andrew John Gjevre
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Primary Examiner(s)Lam, David
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Application NumberUS13/042,508Publication NumberTime in Patent Office462 DaysField of Search365/115, 365/118, 365/120, 365/148, 365/171, 365/173, 365/158, 257324-327, 257497-498US Class Current365/148CPC Class CodesG11C 11/1659 Cell accessG11C 11/1675 Writing or programming circ...
