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Transmission gate-based spin-transfer torque memory unit

  • US 8,199,563 B2
  • Filed: 05/31/2011
  • Issued: 06/12/2012
  • Est. Priority Date: 07/10/2008
  • Status: Active Grant
First Claim
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1. A memory unit comprising:

  • a magnetic tunnel junction data cell configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell; and

    a NMOS transistor in parallel electrical connection with a PMOS transistor, the NMOS transistor and the PMOS transistor electrically connected with the magnetic tunnel junction data cell, a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.

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