Nonvolatile memory device for preventing program disturbance and method of programming the nonvolatile memory device

• US 8,199,584 B2
• Filed: 01/13/2011
• Issued: 06/12/2012
• Est. Priority Date: 07/04/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Jong-Yeol
• Primary Examiner(s): PHUNG, ANH K
• Application Number:
  US13/006,032
• Publication Number:
  US 20110110159A1
• Time in Patent Office: 516 Days
• Field of Search: 365/185.23, 365/185.22, 365/185.17
• US Class Current: 365/185.23
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells

Abstract

A nonvolatile memory device for preventing program disturbances includes a memory cell array block, a word line driver, and a well bias control unit. The memory cell array block includes at least one cell string having a plurality of memory cells serially connected to a bit line and alternately connected to even word lines and odd word lines. After a program verification, the word line driver drives the even word lines with a first voltage and then the odd word lines with the first voltage to drop the even word line to a voltage lower than the first voltage. The well bias control unit floats a bias of a p-well formed by high voltage NMOS transistors that apply corresponding driving voltages to the even word lines and the odd word lines according to an operation mode of a program operation, a read operation, and an erase operation.

Claims

1. A nonvolatile memory device comprising:

a memory cell array block comprising at least one cell string in which a plurality of memory cells are serially connected to a bit line;

a plurality of even word lines and odd word lines alternately connected to the plurality of memory cells; and

a word line driver configured to wait until a program verification read step has been performed on the memory cells and then drive the even word lines with a first voltage and then drive the odd word lines with the first voltage and then drop the even word lines to a voltage that is lower than the first voltage.

2. The nonvolatile memory device of claim 1, wherein the even word line is dropped to a voltage that is lower than the first voltage as a result of driving the even word lines with the first voltage and then driving the off word lines with the first voltage.

3. The nonvolatile memory device of claim 1, wherein the first voltage is a ground voltage.

4. The nonvolatile memory device of claim 1, further comprising a pass transistor unit comprising one or more high voltage NMOS transistors that apply corresponding driving voltages to the even word lines and the odd word lines according to an operation mode of a program operation, a read operation, or an erase operation.

5. The nonvolatile memory device of claim 4, further comprising a well bias control unit configured to float a bias of a p-well formed by the high voltage NMOS transistors after the odd word lines are driven by the first voltage in the program verification read step.

6. The nonvolatile memory device of claim 5, wherein the well bias control unit biases the p-well formed by the high voltage NMOS transistors to a ground voltage during an operation mode of the program operation, the read operation, or the erase operation.

7. The nonvolatile memory device of claim 1, wherein, the word line driver is configured to drive a word line of the plurality of even word lines and odd word lines of a selected memory cell of the plurality of memory cells with a program voltage when it is not determined that the selected memory cell is correctly programmed during the program verification read step.

8. The nonvolatile memory device of claim 1, wherein the plurality of memory cells are NAND flash memory cells.