Multiple time programmable non-volatile memory element

• US 8,199,590 B1
• Filed: 09/24/2010
• Issued: 06/12/2012
• Est. Priority Date: 09/25/2009
• Status: Active Grant

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Novocell Semiconductor, Inc. (Microchip Technology Incorporated)
• Inventors: Novosel, Walter, Sieg, Ethan, Novosel, David, Fiscus, Timothy
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US12/889,653
• Time in Patent Office: 627 Days
• Field of Search: 365/189.2, 365/230.03
• US Class Current: 365/189.2
• CPC Class Codes: G11C 17/16 using electrically-fusible links

Abstract

A multiple time programmable non-volatile memory element and associated programming methods that allow for integration of non-volatile memory with other CMOS integrated circuitry utilizing standard CMOS processing. The multiple time programmable non-volatile memory element includes a capacitor, an access transistor that is electrically coupled to the capacitor at a connection node, and a plurality of one time programmable non-volatile memory cells. Each of the plurality of one time programmable non-volatile memory cells is electrically coupled to the connection node and includes a select transistor that is electrically coupled to an antifuse element. The antifuse element is configured to have changed resistivity in response to one or more voltage pulses received at the connection node, the change in resistivity representing a change in logic state.

Claims

1. A non-volatile memory, comprising:

a plurality of multiple time programmable non-volatile memory elements, each respective multiple time programmable non-volatile memory element including;

a capacitor;

an access transistor electrically coupled to the capacitor at a connection node; and

a plurality of one time programmable non-volatile memory cells corresponding in number to a number of times the respective multiple time programmable non-volatile memory element can be programmed to have a logic state that is either one of a first logic state and a second logic state that is logically opposite the first logic state, each of the plurality of one time programmable non-volatile memory cells being electrically coupled in parallel with one another to the connection node and including a select transistor that is electrically coupled to an antifuse element, the antifuse element being configured to have changed resistivity in response to one or more voltage pulses received at the connection node, the change in resistivity representing a change in the logic state of the respective multiple time programmable non-volatile memory element.

2. The non-volatile memory of claim 1, wherein the select transistor is electrically coupled between the connection node and the antifuse element in each of the plurality of one time programmable non-volatile memory cells.

3. The multiple time programmable non-volatile memory element of claim 2, wherein the antifuse element is an antifuse element transistor having a gate that is connected to the select transistor in each of the plurality of one time programmable non-volatile memory cells.

4. The multiple time programmable non-volatile memory element of claim 2, wherein the select transistor has a drain and a source, and wherein the drain of the select transistor is connected to the connection node and the source of the select transistor is connected to the antifuse element in each of the plurality of one time programmable non-volatile memory cells.

5. The multiple time programmable non-volatile memory element of claim 4, wherein the antifuse element is an antifuse element transistor having a gate that is connected to the source of the select transistor in each of the plurality of one time programmable non-volatile memory cells.

6. The multiple time programmable non-volatile memory element of claim 5, wherein each respective one time programmable non-volatile memory cell of the plurality of programmable non volatile memory cells of the respective multiple time programmable non-volatile memory element can be individually selected and programmed to have either one of the first logic state and the second logic state independently of any other one time programmable non-volatile memory cell of the plurality of one time programmable non-volatile memory cells of the respective multiple time programmable non-volatile memory element.

7. The multiple time programmable non-volatile memory element of claim 4, wherein the antifuse element is an antifuse element transistor having a source and a drain that are connected together and to the source of the select transistor in each of the plurality of one time programmable non-volatile memory cells.

8. The multiple time programmable non-volatile memory element of claim 1, wherein one of a source and a drain of the access transistor is electrically coupled to the capacitor at the connection node.

9. The multiple time programmable non-volatile memory element of claim 1, wherein the antifuse element is electrically coupled between the connection node and the select transistor in each of the plurality of one time programmable non-volatile memory cells.

10. The multiple time programmable non-volatile memory element of claim 9, wherein the antifuse element is an antifuse element transistor having a gate, a source and a drain, and wherein the gate of the antifuse element transistor is connected to the connection node and the source and drain of the antifuse element transistor are connected together and to the select transistor in each of the plurality of one time programmable non-volatile memory cells.

11. The multiple time programmable non-volatile memory element of claim 10, wherein the select transistor has a source and a drain, and wherein one of the source and the drain of the select transistor is connected to the source and drain of the antifuse element in each of the plurality of one time programmable non-volatile memory cells.

12. The multiple time programmable non-volatile memory element of claim 10, wherein the select transistor has a source and a drain, and wherein the drain of the select transistor is connected to the source and drain of the antifuse element in each of the plurality of one time programmable non-volatile memory cells.

13. The multiple time programmable non-volatile memory element of claim 12, wherein each respective one time programmable non-volatile memory cell of the plurality of programmable non volatile memory cells of the respective multiple time programmable non-volatile memory element can be individually selected and programmed to have either one of the first logic state and the second logic state independently of any other one time programmable non-volatile memory cell of the plurality of one time programmable non-volatile memory cells of the respective multiple time programmable non-volatile memory element.

14. The multiple time programmable non-volatile memory element of claim 1, wherein each respective one time programmable non-volatile memory cell of the plurality of programmable non volatile memory cells of the respective multiple time programmable non-volatile memory element can be individually selected and programmed to have either one of the first logic state and the second logic state independently of any other one time programmable non-volatile memory cell of the plurality of one time programmable non-volatile memory cells of the respective multiple time programmable non-volatile memory element.