Memory with output control

• US 8,199,598 B2
• Filed: 09/15/2010
• Issued: 06/12/2012
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Oh, HakJune, Pyeon, Hong Beom, Kim, Jin-Ki
• Primary Examiner(s): Auduong, Gene
• Application Number:
  US12/882,931
• Publication Number:
  US 20110002171A1
• Time in Patent Office: 636 Days
• Field of Search: 365/221, 365/219, 365/230.05, 365/185.11, 365/185.15, 365/185.17, 365/185.33, 365/189.04
• US Class Current: 365/221
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

Abstract

An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Claims

1. A system comprising:

a plurality of serially connected flash memory devices each having a one-side pad architecture, the plurality of flash memory devices including;

a first flash memory device having at least one data input port, at least one data output port, a plurality of control ports, and the first flash memory device being configured to receive data and control signals from an external source; and

a second flash memory device having at least one data input port, at least one data output port, a plurality of control ports, and the second flash memory device being configured to receive data and control signals from one of a different flash memory device of the plurality of flash memory devices and the first flash memory device, and the second flash memory device being configured to provide data and control signals to the external source.

2. The system of claim 1, wherein the plurality of control ports of the first flash memory device include a plurality of input control ports and a plurality of output control ports, and the plurality of control ports of the second flash memory device include a plurality of input control ports and a plurality of output control ports.

3. The system of claim 2, wherein the plurality of output control ports of the first flash memory device are configured to echo values received by the first flash memory device to a next flash memory device.

4. The system of claim 1, wherein the external source is a memory controller.

5. The system of claim 1, wherein a single clock signal is communicated to each of the plurality of flash memory devices.

6. The system of claim 5, wherein the system is configured to delay an output of the system by a predetermined latency.

7. The system of claim 1, wherein the number of flash memory devices is four.

8. The system of claim 7, wherein the four flash memory devices are in a single stack.

9. The system of claim 1, wherein the plurality of flash memory devices are in a single stack.

10. The system of claim 1, wherein each of the plurality of flash memory devices is a NAND flash memory device.

11. The system of claim 1, wherein each of the plurality of flash memory devices have a same memory capacity.

12. The system of claim 1, wherein each of the plurality of flash memory devices include a PLL or DLL.

13. The system of claim 1, wherein each of the plurality of flash memory devices utilizes a maximum of eleven pins.

14. The system of claim 1, wherein each of the plurality of flash memory devices is a synchronous flash memory device.

15. The system of claim 14, wherein the system is configured to delay an output of the system by a predetermined latency.

16. Apparatus comprising:

a package having pins on a side of the package, the pins including all input signal pins and all output signal pins of the package; and

a chip having a flash memory bank and a serial link interface within the package, and the serial link interface having input ports for receiving input signals from at least some of the input signal pins and output ports for providing output signals to at least some of the output signal pins.

17. The apparatus as claimed in claim 16, wherein the pins further include all power supply pins of the package.

18. The apparatus of claim 16, wherein the chip is a first chip, the input ports are first input ports, and the output ports are first output ports, and

the apparatus further comprising a second chip having second input ports capable of receiving read data of the first chip from the first output ports, and second output ports capable of providing the read data to some of the output signal pins.

19. The apparatus of claim 18, wherein the first chip and the second chip are arranged in a stacked formation.

20. The apparatus of claim 16, wherein the package includes additional pins on another side of the package opposite to the side.

21. The apparatus of claim 20, wherein the chip has no connections to the additional pins.