Method and apparatus for processing supplemental and non supplemental assignments

• US 8,199,661 B2
• Filed: 10/27/2006
• Issued: 06/12/2012
• Est. Priority Date: 10/27/2005
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Barriac, Gwendolyn D.
• Primary Examiner(s): Ferris, Derrick
• Assistant Examiner(s): GHOWRWAL, OMAR J
• Application Number:
  US12/091,500
• Publication Number:
  US 20090219840A1
• Time in Patent Office: 2,055 Days
• Field of Search: 370/229, 370/230, 370/241, 370/252, 370276-277, 370/281, 370/295, 370/310, 370/328, 370/329, 370/351, 370/389
• US Class Current: 370/252
• CPC Class Codes: H04B 7/216 Code division or spread-spectrum multiple access [CDMA, SSMA]
• CPC Class Codes: H04B 7/2628 using code-division multiple access [CDMA] or spread spectrum multiple access [SSMA] H04B7/2618 takes precedence
• CPC Class Codes: H04J 13/00 Code division multiplex systems for frequency hopping H04B1/713
• CPC Class Codes: H04L 27/2601 Multicarrier modulation systems
• CPC Class Codes: H04L 5/0057 Physical resource allocation for CQI
• CPC Class Codes: H04W 24/02 Arrangements for optimising operational condition
• CPC Class Codes: H04W 52/146 Uplink power control
• CPC Class Codes: H04W 52/16 Deriving transmission power values from another channel
• CPC Class Codes: H04W 52/325 Power control of control or pilot channels
• CPC Class Codes: H04W 52/48 during retransmission after error or non-acknowledgment
• CPC Class Codes: H04W 52/58 Format of the TPC bits
• CPC Class Codes: H04W 72/0473 the resource being transmission power
• CPC Class Codes: H04W 72/542 using measured or perceived quality
• CPC Class Codes: Y02D 30/00 Reducing energy consumption in communication networks

Abstract

A method and apparatus for processing supplemental and non supplement assignments in a wireless communication system are described. A forward link assignment block (FLAB) is received from a shared signaling medium access control (SS MAC) protocol. It is determined if a medium access control identity (MAC ID) of the FLAB is equal to the MAC ID of an access terminal and it is determined if a supplemental field of a FLAB is equal to ‘1’.

Claims

1. A method of processing supplemental and non supplemental assignments of hop-ports for an access terminal in a wireless communication system, comprising:

receiving a forward link assignment block (FLAB) according to a shared signaling medium access control (SS MAC) protocol;

determining if a medium access control identity (MAC ID) of the FLAB is equal to a MAC ID of an access terminal;

clearing an access terminal assignment (ATA) on an interlace and adding hop-ports specified by a channel identity (ChID) in the FLAB to the ATA for the interlace;

determining if a duplex mode is a frequency division duplex (FDD);

determining if an extended transmission field of the FLAB is equal to 1;

expiring, based upon determining that the extended transmission field of the FLAB is equal to 1, the ATA except for an extended transmission duration assignment ATA which does not overlap in time with a new assignment.

2. The method of claim 1 further comprising:

expiring, based upon determining that the extended transmission field of the FLAB is not equal to 1, the extended transmission duration assignment ATA.

3. The method of claim 1 further comprising:

providing hop-ports specified by the ChID in the FLAB to the ATA in the corresponding interlace, after expiring the ATA.

4. The method of claim 1 further comprising:

providing hop-ports specified by the ChID in the FLAB to the ATA in the corresponding interlace, after expiring the extended transmission duration assignment ATA.

5. The method of claim 1, further comprising:

determining if a supplemental field of the FLAB is equal to 1; and

providing a new ATA on an interlace by including a union of hop-ports in an old ATA in response to determining the supplemental field of the FLAB is equal to 1.

6. The method of claim 5, further comprising:

replacing, in response to determining that the supplemental field of the FLAB is not equal to 1, the ATA with hop-ports specified by the ChID in the FLAB to the ATA for the interlace.

7. A non-transitory computer readable medium communicatively coupled to a processor, the medium including instructions stored thereon, wherein the instructions are executed by the processor, comprising:

a first set of instructions for receiving a forward link assignment block (FLAB) according to a shared signaling medium access control (SS MAC) protocol;

a second set of instructions for determining if a medium access control identity (MAC ID) of the FLAB is equal to a MAC ID of an access terminal;

a third set of instructions for clearing an access terminal assignment (ATA) on an interlace and adding hop-ports specified by a channel identity (ChID) in the FLAB to the ATA for the interlace;

a fourth set of instructions for determining if a duplex mode is a frequency division duplex (FDD);

a fifth set of instructions for determining if an extended transmission field of the FLAB is equal to 1;

a sixth set of instructions for expiring, based upon determining that the extended transmission field of the FLAB is equal to 1, the ATA except for an extended transmission duration assignment ATA which does not overlap in time with a new assignment.

8. The non-transitory computer readable medium of claim 7, further comprising:

a seventh set of instructions for determining if a supplemental field of the FLAB is equal to 1; and

an eighth set of instructions for replacing an ATA for the interlace with the hop-ports specified by the ChID in the FLAB to the ATA for the interlace, in response to determining that the supplemental field of the FLAB is not equal to 1.

9. The non-transitory computer-readable medium of claim 8, further comprising:

a ninth set of instructions providing a new ATA for the interlace by including a union of hop-ports in an old ATA in response to determining the supplemental field of the FLAB is equal to 1.

10. An apparatus operable in a wireless communication system, comprising:

at least one processor executing instructions comprising;

receiving a forward link assignment block (FLAB) according to a shared signaling medium access control (SS MAC) protocol;

determining if a medium access control identity (MAC ID) of the FLAB is equal to a MAC ID of an access terminal;

clearing an access terminal assignment (ATA) on an interlace and add hop-ports specified by a channel identity (ChID) in the FLAB to the ATA for the interlace;

determining if a duplex mode is frequency division duplex (FDD) after clearing the ATA and adding the hop ports; and

determining, based upon determining the duplex mode is a FDD, if an extended transmission field of the FLAB is equal to 1;

expiring, based upon determining that the extended transmission field of the FLAB is equal to 1, the ATA except for an extended transmission duration assignment ATA which does not overlap in time with a new assignment.

11. The apparatus of claim 10 the instructions further comprising:

expiring the extended transmission duration assignment ATA.

12. The apparatus of claim 11, the instructions further comprising:

providing hop-ports specified by the ChID in the FLAB to the ATA in the corresponding interlace, after expiring the extended transmission duration assignment ATA.

13. The apparatus of claim 10 the instructions further comprising:

providing hop-ports specified by the ChID in the FLAB to the ATA in the corresponding interlace, after expiring the ATA.

14. The apparatus of claim 10;

the instructions further comprising;

replacing the ATA with the hop-ports specified by the ChID in the FLAB to the ATA for the interlace.

15. The apparatus of claim 10, the instructions further comprising:

determining if a supplemental field of the FLAB is equal to 1; and

providing a new ATA on the interlace by including a union of hop-ports in an old ATA in response to determining the supplemental field of the FLAB is equal to 1.

16. A system for processing supplemental and non supplemental assignments of hop-ports in a wireless communication system, comprising:

an access terminal further comprising;

a processor;

a non-transitory computer-readable storage medium communicatively coupled to the processor and storing computer executable components executed by the processor, wherein the processor is configured to;

receive a forward link assignment block (FLAB) according to a shared signaling medium access control (SS MAC) protocol;

determine if a medium access control identity (MAC ID) of the FLAB is equal to a MAC ID of an access terminal;

clear an access terminal assignment (ATA) on an interlace and add hop-ports specified by a channel identity (ChID) in the FLAB to the ATA for the interlace;

determine whether a duplex mode is a frequency division duplex (FDD) after the ATA is cleared and the hop ports added;

determine, based upon determining the duplex mode is a FDD, if an extended transmission field of the FLAB is equal to 1; and

expire, based upon the determination that the extended transmission field of the FLAB is equal to 1, the ATA except for an extended transmission duration assignment ATA which does not overlap in time with a new assignment.

17. The system of claim 16, the processor is further configured to:

expire, based upon the determination that the extended transmission field of the FLAB is not equal to 1, the extended transmission duration assignment ATA.

18. The system of claim 16, the processor is further configured to:

provide hop-ports specified by the ChID in the FLAB to the ATA in the corresponding interlace, after expiration of the ATA.

19. The system of claim 16, the processor is further configured to:

provide hop-ports specified by the ChID in the FLAB to the ATA in the corresponding interlace, after expiration of the extended transmission duration assignment ATA.

20. The system of claim 16, the processor is further configured to determine if a supplemental field of the FLAB is equal to 1.

21. The system of claim 20, the processor is further configured to provide a new ATA on the interlace by including a union of hop-ports in an old ATA in response to the determination that the supplemental field of the FLAB is equal to 1.

22. The system of claim 21, the processor is further configured to replace, in response to the determination that the supplemental field of the FLAB is not equal to 1, the ATA with the hop-ports specified by the ChID in the FLAB to the ATA for the interlace.