Edge-based sampler offset correction

• US 8,199,866 B2
• Filed: 02/11/2008
• Issued: 06/12/2012
• Est. Priority Date: 02/12/2007
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Fuller, Andrew M., Poulton, John
• Primary Examiner(s): Joseph, Jaison
• Application Number:
  US12/525,044
• Publication Number:
  US 20100220828A1
• Time in Patent Office: 1,583 Days
• Field of Search: 375/355, 375/359, 375/360, 375/371, 375/373
• US Class Current: 375/355
• CPC Class Codes: H03F 2203/45008 the addition of two signals being made by a resistor addition circuit for producing the common mode signal
• CPC Class Codes: H03F 2203/45306 the common gate stage implemented as dif amp eventually for cascode dif amp
• CPC Class Codes: H03F 2203/45588 the IC comprising offset compensating means
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H04L 25/0278 Arrangements for impedance matching
• CPC Class Codes: H04L 25/063 Setting decision thresholds using feedback techniques only
• CPC Class Codes: H04L 7/046 using a dotting sequence

Abstract

Embodiments of a circuit are described. This circuit includes a receiver circuit including a first sampler (312-1) and a second” sampler (312-2). A clock-data-recovery circuit (324) in the receiver circuit adjusts a sample time of the receiver circuit so that the sample time is proximate to a signal crossing point at an edge of an eye pattern associated with received signals. An offset-calibration circuit (326) in the receiver circuit determines and adjusts an offset voltage of a given sampler, which can be the first sampler or the second sampler. This offset-calibration circuit may determine a present offset voltage (412) of the given sampler in a timing region proximate to the signal crossing point (410-2) in which the clock-data-recovery circuit dithers about a present sample time based on the present offset voltage. Additionally, the clock-data-recovery circuit and the offset-calibration circuit may iteratively converge on the signal crossing point and a residual offset voltage of the given sampler.

Claims

1. A receive circuit, comprising:

a receiver that samples a signal, the receiver comprising a first sampler that samples a voltage level associated with an expected edge of the signal and a second sampler that samples digital values represented by the signal, the samplers collectively generating a set of at least three samples associated with each one of plural edge crossings in the signal;

a phase alignment circuit that detects an edge of the signal; and

an offset-calibration circuit coupled to the phase alignment circuit to correct, responsive to correlation of specific signal patterns with edge timing represented by the signal, receiver voltage offset associated with sampling the signal in dependence upon detected correlation, wherein the offset-calibration circuit corrects the receiver voltage offset by varying the receiver voltage offset by a first polarity if a correlation is detected that indicates that an actual edge tends to be early with respect to an expected edge for a first signal transition and late with respect to an expected edge for a second signal transition, and by a second polarity if correlation is detected that indicates that the actual edge tends to be late with respect to the expected edge for the first signal transition and early with respect to the expected edge for the second signal transition.

2. The receive circuit of claim 1, where the offset-calibration circuit corrects for receiver voltage offset to urge the sampler toward a level where specific signal transitions are not correlated with an early or late edge timing, to thereby cause the phase alignment circuit to dither about an expected data transition edge notwithstanding inherent receiver voltage offset associated with sampling of the signal.

3. The receive circuit of claim 1, where:

the offset-calibration circuit corrects receiver voltage offset by increasing an effective receiver sampling threshold in response to (i) correlation of an early edge crossing with a low-to-high logic transition and (ii) correlation of a late edge crossing with a high-to-low logic transition; and

the offset-calibration circuit corrects receiver voltage offset by decreasing the effective receiver sampling threshold in response to (iii) correlation of a late edge crossing with a low-to-high logic transition and (iv) correlation of an early edge crossing with a high-to-low logic transition.

4. The receive circuit of claim 1, where the two samplers sample the signal using a phase separation of approximately ninety degrees.

5. The receive circuit of claim 1, further comprising:

means for switching roles of the two samplers; and

means for correcting offset for each of the two samplers during a calibration mode.

6. The receive circuit of claim 1, where the signal is a binary signal.

7. The receive circuit of claim 1, embodied as a memory device.

8. The receive circuit of claim 1, embodied as a memory controller.

9. The receive circuit of claim 1, further comprising a mode in which voltage offset is calibrated and corrected.

10. The receive circuit of claim 1, wherein the phase alignment circuit is part of a clock recovery circuit that recovers the receiver clock from the signal.

11. A receive circuit, comprising:

a first sampler to sample edge crossings of a signal;

a second sampler to sample data values of the signal;

a phase adjustment circuit to generate an adjusted phase based upon sampled edge crossings and to provide the adjusted phase to the second sampler to time the sampling of the data values; and

an offset-calibration circuit to provide a voltage offset correction to adjust the sampling of edge crossings by the second sampler;

where the offset-calibration circuit is adapted to respond to correlation between specific data value transition patterns and timing of edge crossings by adjusting the voltage offset correction in an iterative manner to reduce detected correlation, where the offset-calibration circuit corrects the voltage offset by varying the voltage offset by a first polarity if a correlation is detected that indicates that an actual edge tends to be early with respect to an expected edge for a first signal transition and late with respect to an expected edge for a second signal transition, and by a second polarity if correlation is detected that indicates that the actual edge tends to be late with respect to the expected edge for the first signal transition and early with respect to the expected edge for the second signal transition; and

where the phase adjustment circuit is adapted to converge on an edge crossing point of the signal based upon the voltage offset correction.

12. The receive circuit of claim 11, where the first sampler and the second sampler are controlled to perform sampling at relative times defined by a fixed receiver clock phase difference.

13. The receive circuit of claim 12, where the fixed receiver clock phase difference is ninety degrees.

14. A receive circuit, comprising:

a phase detector to adjust a clock phase dependent upon a signal edge crossing;

an offset-calibration circuit to correct voltage offset to adjust voltage level of the edge crossing relative to the signal in response to correlation between (i) early/late tendencies of the signal with respect to the expected edge crossing, and (ii) at least one specific signal transition pattern, the offset-calibration circuit;

a first sampler to sample the signal using the clock phase;

a second sampler used to sample edge crossings, where the offset-calibration circuit is coupled to the second sampler to correct voltage offset in the second sampler; and

circuitry for switching the role of each of the samplers, to alternatively correct voltage offset in each of the samplers.

15. The receive circuit of claim 14, where the phase detector is an Alexander phase detector.

16. The receive circuit of claim 14 embodied in a system, the system also comprising memory and control logic, the memory to store information representing edge samples, the control logic to detect the correlation from the information stored in the memory and to control the offset-cancelation circuit to correct voltage offset.

17. A method of determining an voltage offset in a receiver circuit, comprising:

detecting data level transitions in a digital signal;

detecting data edges in the digital signal;

detecting occurrence of at least one predetermined pattern based on the data level transitions; and

monitoring correlation between an early/late tendency of the data edge and at least one predetermined signal pattern, and responsively adjusting voltage offset associated with detecting the data edges, wherein adjusting the voltage offset comprises varying the voltage offset by a first polarity if a correlation is detected that indicates that an actual edge tends to be early with respect to an expected edge for a first signal transition and late with respect to an expected edge for a second signal transition, and by a second polarity if correlation is detected that indicates that the actual edge tends to be late with respect to the expected edge for the first signal transition and early with respect to the expected edge for the second signal transition.

18. The method of claim 17, where detecting data edges includes detecting data edges based on adjusted voltage offset, and where the method further comprises generating a receiver clock based upon adjusted voltage offset.

19. The method of claim 17, further comprising using multiple samplers, selectively reassigning sampler function for use in sampling data edges, and independently adjusting voltage offset of each samplers to independently for each sampler reduce correlation between an early/late tendency of the data edge with at least one predetermined signal pattern.

20. A method, comprising:

sampling edge crossings of a signal;

sampling data values of the signal;

adjusting phase based upon sampled edge crossings and using the adjusted phase to time the sampling of the data values; and

detecting correlation between specific data value transition patterns and timing of edge crossings;

adjusting voltage offset associated with sampling of the edge crossings in an iterative manner to reduce detected correlation, wherein adjusting the voltage offset comprises varying the voltage offset by a first polarity if a correlation is detected that indicates that an actual edge tends to be early with respect to an expected edge for a first signal transition and late with respect to an expected edge for a second signal transition, and by a second polarity if correlation is detected that indicates that the actual edge tends to be late with respect to the expected edge for the first signal transition and early with respect to the expected edge for the second signal transition; and

converging on an edge crossing point of the signal based upon the voltage offset correction.

21. An apparatus comprising instructions stored on machine-readable media, the instructions, when executed, adapted to cause a machine to:

detect data level transitions in a digital signal;

detect data edges in the digital signal;

detect occurrence of at least one predetermined pattern based on the data level transitions;

monitor correlation between an early/late tendency of the data edge with at least one predetermined signal pattern; and

responsive to correlation, adjust voltage offset associated with detecting the data edges, wherein adjusting the voltage offset comprises varying the voltage offset by a first polarity if a correlation is detected that indicates that an actual edge tends to be early with respect to an expected edge for a first signal transition and late with respect to an expected edge for a second signal transition, and by a second polarity if correlation is detected that indicates that the actual edge tends to be late with respect to the expected edge for the first signal transition and early with respect to the expected edge for the second signal transition.

22. A computer-readable medium containing data representing a receive circuit, where the receive circuit includes:

a phase detector to adjust a clock phase dependent upon a signal edge crossing;

an offset-calibration circuit to correct voltage offset in response to correlation between (i) early/late tendencies of the signal with respect to the expected edge crossing, and (ii) at least one specific signal transition pattern, the offset-calibration circuit correcting voltage offset to adjust voltage level of the edge crossing relative to the signal;

a first sampler to sample an input signal using the clock phase;

a second sampler used to sample edge crossings, where the offset-calibration circuit is coupled to the second sampler to correct voltage offset in the second sampler; and

circuitry for switching the role of each of the samplers, to alternatively correct voltage offset in each of the samplers.

23. The computer-readable medium of claim 22, where the receive circuit is embodied in a memory controller that includes memory and control logic, the memory to store information representing edge samples, the control logic to detect the correlation from the information stored in the memory and to control the offset-cancelation circuit to correct voltage offset.

24. The computer-readable medium of claim 23, where the control logic is at least partially embodied as instructional logic.