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Entry/exit control to/from a low power state in a complex multi level memory system

  • US 8,201,004 B2
  • Filed: 09/14/2007
  • Issued: 06/12/2012
  • Est. Priority Date: 09/14/2006
  • Status: Expired
First Claim
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1. A power control apparatus comprising:

  • a programmable global power controller, wherein said programmable global power controller is operable to reduce the power consumption in said logic blocks in response to detecting a lack of activity within said logic blocks;

    a plurality of local power controllers; and

    a plurality of logic blocks to be controlled, wherein at least one of said programmable global power controller and said plurality of local power controllers perform handshaking to determine the power status for at least one of said plurality of logic blocks and said plurality of local power controllers.

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