Table-based DFM for accurate post-layout analysis

• US 8,201,111 B2
• Filed: 08/02/2011
• Issued: 06/12/2012
• Est. Priority Date: 10/13/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hou, Yung-Chin, Cheng, Ying-Chou, Liu, Ru-Gun, Lai, Chih-Ming, Cheng, Yi-Kan, Lin, Chung-Kai, Chao, Hsiao-Shu, Yeh, Ping-Heng, Wu, Min-Hong, Ku, Yao-Ching, Ou, Tsong-Hua
• Primary Examiner(s): LEVIN, NAUM B
• Application Number:
  US13/195,907
• Publication Number:
  US 20110289466A1
• Time in Patent Office: 315 Days
• Field of Search: 716 54- 56, 716/132, 700/121
• US Class Current: 716/54
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.

Claims

1. An integrated circuit (IC) design method comprising:

providing a plurality of IC devices with various design dimensions;

collecting electrical performance data of the IC devices;

extracting equivalent dimensions of the IC devices based on the various design dimensions;

generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and

creating a data refinement table using the equivalent dimensions and the electrical performance data;

wherein the extracting, the generating, and the creating are each carried out using a computer hardware device encoded with software instructions.

2. The method of claim 1, further comprising predicting electrical performance of a device using the data refinement table and equivalent dimensions of the device.

3. The method of claim 1, wherein the extracting of the equivalent dimensions comprises:

generating contours of a channel region for one of the IC devices; and

calculating equivalent length and width of the channel region of the corresponding IC device.

4. The method of claim 3, wherein the generating contours comprises using a shape simulation tool.

5. The method claim 1, wherein the generating of the shape related model comprises measuring electrical performance parameters of the IC device.

6. The method claim 1, wherein the generating of the shape related model comprises calculating electrical performance parameters of the IC devices using the equivalent dimensions of the IC devices.

7. The method of claim 1, wherein the generating of the shape related model comprises using one method selected from the group consisting of multiple regression, linear quadratic modeling, and response surface approximation.

8. The method of claim 1, wherein the creating of the data refinement table comprises finding sensitivity parameters of the electrical performance relative to the equivalent dimensions for said each of the IC devices.

9. The method of claim 8, wherein the finding the sensitivity coefficients comprises:

finding a width sensitivity of an electrical parameter for said each of the IC devices; and

finding a length sensitivity of the electrical parameter for said each of the IC devices.

10. The method of claim 9, wherein the electrical parameter comprises a parameter selected from the group consisting of saturation current, leakage current, and threshold voltage.

11. An apparatus comprising a non-transitory, tangible computer readable storage medium storing a computer program, wherein the computer program has instructions that when executed by a computer, carry out:

obtaining a design layout having design dimensions of a IC device;

collecting electrical performance data of the IC device;

extracting equivalent dimensions of the IC device based on the design layout;

generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC device; and

creating a data refinement table.

12. The apparatus of claim 11, wherein the computer program further includes instructions for predicting electrical performance of the IC device based on the shape related model.

13. The apparatus of claim 11, wherein the computer program further includes instructions for tuning the design layout.

14. The apparatus of claim 11, wherein the instructions for generating of the shape related model include instructions for measuring electrical performance parameters of the IC device.

15. The apparatus of claim 11, wherein the instructions for generating of the shape related model include instructions for calculating electrical performance parameters of the IC device using the equivalent dimensions of the IC device.

16. The apparatus of claim 11, wherein the instructions for creating of the data refinement table include instructions that associate electrical parameters of the data refinement table with the shape related model.

17. An integrated circuit (IC) design method comprising:

receiving an IC device with various design dimensions;

collecting electrical performance data of the IC device;

extracting equivalent dimensions of the IC device based on the various design dimensions;

generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC device;

creating a data refinement table using the shape related model; and

predicting electrical performance of the IC device based on the data refinement table,

wherein the creating and predicting are carried out using a computer hardware device encoded with software instructions.

18. The method of claim 17, wherein the computer program further includes instructions for tuning the design layout.

19. The method of claim 17, wherein the instructions for generating of the shape related model include instructions for measuring electrical performance parameters of the IC device.

20. The method of claim 17, wherein the instructions for generating of the shape related model include instructions for calculating electrical performance parameters of the IC device using the equivalent dimensions of the IC device.