Method of manufacturing electronic component embedded circuit board

• US 8,201,324 B2
• Filed: 01/26/2009
• Issued: 06/19/2012
• Est. Priority Date: 07/21/2008
• Status: Expired due to Fees

• Current Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: Kim, Byoung-Chan, Shin, Young-Hwan, Lee, Jong-Jin
• Primary Examiner(s): ARBES, CARL J
• Application Number:
  US12/359,416
• Publication Number:
  US 20100012364A1
• Time in Patent Office: 1,240 Days
• Field of Search: 298/25, 298/30, 298/32, 298/34, 298/52, 257/686
• US Class Current: 29/830
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/91 Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01075 Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H05K 1/187 : the patterned circuits being prefabricated circuits, which are not yet attached to a permanent insulating substrate, e.g. on a temporary carrier
• CPC Class Codes: H05K 2201/10515 : Stacked components
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 2203/0376 : Etching temporary metallic carrier substrate
• CPC Class Codes: H05K 2203/1469 : Circuit made after mounting or encapsulation of the components
• CPC Class Codes: H05K 3/205 : using a pattern electroplated or electroformed on a metallic carrier
• CPC Class Codes: H05K 3/4602 : characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
• CPC Class Codes: Y10T 29/49117 : Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49133 : with component orienting
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base

Abstract

An electronic component embedded printed circuit board and a method for manufacturing the same are disclosed. The method includes: providing a first carrier having a first circuit pattern formed on one surface thereof; providing a second carrier having a second circuit pattern formed on one surface thereof; flip-chip bonding an electronic component to the first circuit pattern; stacking one side of an insulator on one side of the first carrier to cover the electronic component; compressing the second carrier having the second circuit pattern formed on one surface thereof on an other side of the insulator; and removing the first carrier and the second carrier. The method can improve the degree of conformation for an electrical component by embedding the electrical component using a flip-chip bonding method and can improve the yield by simplifying the production process.

Claims

1. A method of manufacturing an electronic component embedded printed circuit board, the method comprising:

providing a first carrier having a first circuit pattern formed on one surface thereof;

providing a second carrier having a second circuit pattern formed on one surface thereof;

flip-chip bonding an electronic component to the first circuit pattern;

stacking one side of an insulator on one side of the first carrier to cover the electronic component;

compressing the second carrier having the second circuit pattern formed on one surface thereof on an other side of the insulator; and

removing the first carrier and the second carrier,

wherein the providing of the first carrier having the first circuit pattern formed on one surface thereof and the providing of the second carrier having the second circuit pattern formed on one surface thereof are performed simultaneously through;

providing the first carrier and the second carrier coupled together with an adhesive layer formed by a material, which has a flexible adhesive strength being changed by temperature;

forming the first circuit pattern on the first carrier and the second circuit pattern on the second carrier through electroplating; and

separating the first carrier and the second carrier.

2. The method of claim 1, wherein the electronic component is flip-chip bonded with the first circuit pattern using a solder bump or a gold stud bump.

3. The method of claim 1, wherein:

a first seed layer is formed on one side of the first carrier, the first seed layer being made of a different material from that of the first carrier; and

the removing of the first carrier comprises removing the first seed layer.

4. A method of manufacturing an electronic component embedded printed circuit board, the method comprising:

providing a first carrier having a first circuit pattern formed on one surface thereof;

flip-chip bonding a first electronic component to the first circuit pattern;

stacking a first insulator on one side of the first carrier to cover the first electronic component;

providing a second carrier having a second circuit pattern formed on one surface thereof;

flip-chip bonding a second electronic component to the second circuit pattern;

stacking a second insulator on one side of the second carrier to cover the second electronic component;

compressing the first insulator and the second insulator such that the first electronic component and the second electronic component face each other; and

removing the first carrier and the second carrier,

wherein the providing of the first carrier having the first circuit pattern formed on one surface thereof and the providing of the second carrier having the second circuit pattern for on one surface thereof are performed simultaneously through;

providing and the second carrier coupled together with an adhesive layer formed by a material, which has a flexible adhesive strength being changed by temperature;

forming the first circuit pattern on the first carrier and the second circuit pattern on the second carrier through electroplating; and

separating a first carrier and the second carrier.

5. The method of claim 4, wherein the first electronic component is flip-chip bonded with the first circuit pattern by using a solder bump or a gold stud bump.

6. The method of claim 4, wherein:

a first seed layer is formed on one side of the first carrier, the first seed layer being made of a different material from that of the first carrier; and

the removing of the first carrier comprises removing the first seed layer.