Method of manufacturing transistor

• US 8,202,782 B2
• Filed: 08/29/2008
• Issued: 06/19/2012
• Est. Priority Date: 09/05/2007
• Status: Expired due to Fees

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Meunier-Bellard, Philippe, Heringa, Anco, Donkers, Johannes
• Primary Examiner(s): Kraig, William F
• Application Number:
  US12/676,017
• Publication Number:
  US 20100176426A1
• Time in Patent Office: 1,390 Days
• Field of Search: 257/530, 257/E21.336, 257/288, 257/401, 257/900, 257/E21.626, 257/E21.64, 438/760, 438/632, 438/648, 438/184, 438/230, 438/303, 438/596
• US Class Current: 438/303
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/41783 Raised source or drain electrodes self aligned with the gate
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

A method of manufacturing a transistor (300), the method comprising forming a gate (101) on a substrate (102), forming a spacer (201) on lateral side walls of the gate (101) and on an adjacent portion (202) of the substrate (102), modifying material of the spacer (201) so that the modified spacer (301) covers only a lower portion (303) of the lateral side walls of the gate (101), and providing source/drain regions (301) in the modified spacer (301).

Claims

1. A method of manufacturing a transistor, the method comprising

forming a gate on a substrate;

forming a spacer on lateral side walls of the gate and on an adjacent portion of the substrate;

modifying material of the spacer such that the modified spacer covers only a lower portion of the lateral side walls of the gate;

providing source/drain regions in the modified spacer;

wherein the modifying comprises rearranging the material of the spacer so that the rearranged spacer covers only a lower portion of the lateral side walls of the gate and an increased portion of the substrate.

2. The method of claim 1, comprising implanting the source/drain regions in the modified spacer.

3. The method of claim 1, comprising forming the source/drain regions in the modified spacer by making the modified spacer of a doped material.

4. The method of claim 1, wherein the rearranging comprises annealing.

5. The method of claim 4, wherein the annealing is hydrogen annealing.

6. The method of claim 1, wherein the modifying comprises etching back part of the material of the spacer.

7. The method of claim 1, comprising modifying the material of the spacer in such a manner that a thickness of the modified spacer gradually increases towards the gate.

8. The method of claim 1, comprising forming a protection structure, the protection structure being essentially L-shaped in a cross-sectional view, between the gate and the spacer.

9. The method of claim 1, comprising forming the spacer on the lateral side walls of the gate and on the adjacent portion of the substrate by

depositing spacer material over the gate and the substrate;

and

removing part of the spacer material so that the spacer remains only on the lateral side walls of the gate and on the adjacent portion of the substrate.