Method of forming through silicon via with dummy structure

• US 8,202,800 B2
• Filed: 05/20/2011
• Issued: 06/19/2012
• Est. Priority Date: 10/22/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Chih-Hua, Chen, Chen-Shien, Kuo, Chen-Cheng, Shen, Wen-Wei
• Primary Examiner(s): Bryant, Kiesha
• Assistant Examiner(s): Payen, Marvin
• Application Number:
  US13/112,347
• Publication Number:
  US 20110217841A1
• Time in Patent Office: 396 Days
• Field of Search: 438/667, 257/E21.597
• US Class Current: 438/667
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of forming a through silicon via (TSV) structure includes forming an interconnect pad over a substrate. An under layer is formed over the interconnect pad. A vertical conductive post is formed at least partially through the substrate. At least one dummy structure is formed at least partially through the under layer. A top pad is formed over the dummy structure and the vertical conductive post. The top pad covers a wider area than a cross section of the vertical conductive post. The interconnect pad is electrically connected to the top pad. The dummy structure connects the top pad and the under layer thereby fastening the top pad and the interconnect pad.

Claims

1. A method of forming a through silicon via (TSV) structure, said method comprising:

forming an interconnect pad over a substrate;

forming an under layer over the interconnect pad;

forming a vertical conductive post at least partially through the substrate;

forming at least one dummy structure at least partially through the under layer; and

forming a top pad over the dummy structure and the vertical conductive post, wherein the top pad covers a wider area than a cross section of the vertical conductive post, the interconnect pad is electrically connected to the top pad, and the dummy structure connects the top pad and the under layer thereby fastening the top pad and the interconnect pad.

2. The method of claim 1, further comprising etching the under layer to form space for the dummy structure.

3. The method of claim 1, wherein forming the under layer comprises forming a seed layer.

4. The method of claim 1, wherein forming the under layer comprises forming an isolation layer.

5. The method of claim 1, wherein forming the under layer comprises forming a passivation layer.

6. The method of claim 1, wherein forming the under layer comprises forming a dummy interconnect layer.

7. The method of claim 1, further comprising polishing a backside of the substrate to expose the vertical conductive post on the backside.

8. The method of claim 1, further comprising forming a backside interconnect layer below the substrate, wherein the backside interconnect layer is connected to the vertical conductive post.

9. The method of claim 8, further comprising forming an electroless nickel immersion gold (ENIG) layer below the backside interconnect layer.

10. A method of forming a through silicon via (TSV) structure, said method comprising:

forming an interconnect pad over a substrate;

forming an under layer over the interconnect pad, the under layer including an isolation layer;

forming a vertical conductive post at least partially through the substrate;

forming at least one dummy structure at least partially through the under layer;

forming a top pad over the dummy structure and the vertical conductive post, wherein the top pad covers a wider area than a cross section of the vertical conductive post, the interconnect pad is connected to the top pad, and the dummy structure connects the top pad and the under layer thereby fastening the top pad and the interconnect pad; and

polishing a backside of the substrate to expose the vertical conductive post on the backside.

11. The method of claim 10, further comprising forming a backside interconnect layer below the substrate, wherein the backside interconnect layer is connected to the vertical conductive post.

12. The method of claim 10, wherein the formation of the at least one dummy structure comprising forming a plurality of the dummy structures around the vertical conductive post.

13. The method of claim 12, wherein the dummy structures are formed with a uniform distribution in a first area underneath the top pad except a second area occupied by either the vertical conductive post or a connection structure that connects the top pad and the interconnect pad.

14. The method of claim 12, wherein the dummy structures are formed in a square grid pattern.

15. The method of claim 12, wherein the dummy structures are formed in a circular pattern around the vertical conductive post.

16. The method of claim 12, comprising forming a plurality of said dummy structures having a linear shape placed around the vertical conductive post.

17. The method of claim 16, wherein the dummy structures are formed as straight lines.

18. The method of claim 16, wherein the dummy structures are formed to be evenly spaced from each other.

19. The method of claim 16, wherein the dummy structures are formed to have at least two different lengths.

20. A method of forming a through silicon via (TSV) structure, said method comprising;

forming an interconnect pad over a substrate;

forming an under layer over the interconnect pad, the under layer including an isolation layer;

forming a vertical conductive post at least partially through the substrate;

etching the under layer to form space for at least one dummy structure;

forming the at least one dummy structure at least partially through the under layer;

forming a top pad over the dummy structure and the vertical conductive post, wherein the top pad covers a wider area than a cross section of the vertical conductive post, the interconnect pad is connected to the top pad, and the dummy structure connects the top pad and the under layer thereby fastening the top pad and the interconnect pad;

polishing a backside of the substrate to expose the vertical conductive post on the backside; and

forming a backside interconnect layer below the substrate, the backside interconnect layer being connected to the vertical conductive post.