Multi-junction solar cells and methods and apparatuses for forming the same

• US 8,203,071 B2
• Filed: 07/23/2008
• Issued: 06/19/2012
• Est. Priority Date: 01/18/2007
• Status: Expired due to Fees

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Sheng, Shuran, Chae, Yong Kee, Choi, Soo Young, Won, Tae Kyung, Li, Liwei
• Primary Examiner(s): Michener, Jennifer
• Assistant Examiner(s): GARDNER, SHANNON M
• Application Number:
  US12/178,289
• Publication Number:
  US 20090020154A1
• Time in Patent Office: 1,427 Days
• Field of Search: 136/252, 136/255, 136/258, 136/261
• US Class Current: 136/255
• CPC Class Codes: H01L 31/03685 including microcrystalline silicon, uc-Si
• CPC Class Codes: H01L 31/076 Multiple junction or tandem solar cells
• CPC Class Codes: H01L 31/1804 comprising only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 31/1824 Special manufacturing methods for microcrystalline Si, uc-Si
• CPC Class Codes: Y02E 10/545 Microcrystalline silicon PV cells
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells
• CPC Class Codes: Y02E 10/548 Amorphous silicon PV cells
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

Embodiments of the present invention generally relate to solar cells and methods and apparatuses for forming the same. More particularly, embodiments of the present invention relate to thin film multi-junction solar cells and methods and apparatuses for forming the same. Embodiments of the present invention also include an improved thin film silicon solar cell, and methods and apparatus for forming the same, where one or more of the layers in the solar cell comprises at least one amorphous silicon layer that has improved electrical characteristics and mechanical properties, and is capable of being deposited at rates many times faster than conventional amorphous silicon deposition processes.

Claims

1. A tandem junction photovoltaic device, comprising:

a first photovoltaic junction and a second photovoltaic junction, wherein the first photovoltaic junction comprises;

a p-type amorphous silicon layer;

a p-i buffer intrinsic type amorphous silicon layer;

a bulk intrinsic type amorphous silicon layer, wherein the p-i buffer intrinsic type amorphous silicon layer and the bulk intrinsic type amorphous silicon layer are deposited in a single processing chamber by supplying a gas mixture including a silicon containing gas and a hydrogen containing gas, wherein the hydrogen containing gas supplied into the processing chamber is gradually reduced to smoothly transition depositing the p-i buffer intrinsic type amorphous silicon layer to depositing the bulk intrinsic type amorphous silicon layer; and

a n-type microcrystalline silicon layer; and

wherein the second photovoltaic junction comprises;

a p-doped microcrystalline silicon layer;

an intrinsic type microcrystalline silicon layer; and

a n-doped amorphous silicon layer adjacent to the intrinsic type microcrystalline silicon layer.

2. The device of claim 1, further comprising:

an interfacial layer disposed between the first and the second photovoltaic junction.

3. The device of claim 1, wherein the intrinsic type microcrystalline silicon layer is formed by a multiple step deposition process, wherein each deposition step has different hydrogen to silane gas ratio.

4. The device of claim 1, wherein the p-i buffer intrinsic type amorphous silicon layer and the bulk intrinsic type amorphous silicon layer are deposited in a single processing chamber by varying a hydrogen to silane gas ratio.

5. The device of claim 3, wherein the hydrogen to silane gas ratio is decreased in each successive deposition step used to deposit the intrinsic type microcrystalline silicon layer.

6. The device of claim 1, wherein n-doped amorphous silicon layer further comprises:

a first n-doped layer disposed over the intrinsic type microcrystalline silicon layer; and

a second n-doped amorphous layer disposed on the first n-doped layer, wherein the doping level in the second n-doped amorphous layer is greater than the doping level in the first n-doped layer.

7. The device of claim 1, further comprising:

an interfacial layer disposed between the first photovoltaic junction and the second photovoltaic junction, wherein the interfacial layer comprises a material selected from a group consisting of silicon oxynitride, silicon nitride, silicon carbide, silicon oxide, SiOC, and SiCN.

8. The device of claim 1, further comprising:

a lower interfacial layer disposed over the second photovoltaic junction in contact with the n-doped amorphous silicon layer, wherein the n-doped amorphous silicon layer is disposed adjacent to the intrinsic type microcrystalline silicon layer.

9. The device of claim 8, wherein the lower interfacial layer comprises at least one of heavily doped n-type amorphous silicon layer, n-type microcrystalline silicon layer, a n-type amorphous silicon layer, silicon oxynitride, silicon nitride, silicon carbide, silicon oxide, SiOC, or SiCN.

10. The device of claim 1, further comprising:

a first transparent conductive oxide layer disposed over a surface of a substrate; and

a p-type microcrystalline silicon contact layer disposed between the p-type amorphous silicon layer and the first transparent conductive oxide layer.

11. The device of claim 10, wherein:

the first transparent conductive oxide layer comprises zinc and oxygen, and

the p-type microcrystalline silicon contact layer has a thickness between about 20 Å and

about 200 Å

.

12. The device of claim 1, further comprising:

an n-type amorphous silicon buffer layer disposed between the a bulk intrinsic type amorphous silicon layer and the n-type microcrystalline silicon layer, wherein the n-type amorphous silicon buffer layer is between about 10 Å and

about 200 Å

thick and comprises silicon that has a phosphorous dopant concentration between about 1×

10¹⁸ atoms/cm² and about 1×

10²⁰ atoms/cm².

13. The device of claim 1, wherein the p-i buffer intrinsic type amorphous silicon layer is formed by a process comprising:

delivering a silane gas at a second flow rate to the processing volume;

delivering a hydrogen containing gas to the processing volume so that the ratio of the flow rate of the hydrogen containing gas to second flow rate is between about 20 and about 50; and

controlling the pressure in the processing volume to pressure greater than or equal to the first pressure.

14. The device of claim 13, wherein the bulk intrinsic type amorphous silicon layer is formed by a process comprising:

delivering a silane gas at a first flow rate to a processing volume that is adjacent to a surface of the substrate;

delivering a hydrogen containing gas to the processing volume so that the hydrogen to silane dilution ratio is between about 8 and about 15; and

controlling the pressure in the processing volume to a first pressure.

15. The device of claim 1, wherein the p-i buffer intrinsic type amorphous silicon layer has a thickness of less than about 200 Å

.

16. The device of claim 1, wherein the p-i buffer intrinsic type amorphous silicon layer is formed by a process comprising:

delivering the hydrogen containing gas at a hydrogen to silane containing gas ratio that is decreased during the process of forming the p-i buffer intrinsic type amorphous silicon layer.

17. The device of claim 1, wherein

the p-i buffer intrinsic type amorphous silicon layer is formed by delivering a silane containing gas at a hydrogen containing gas at a hydrogen to silane gas ratio of between about 40:

1 and about 20;

1, and

the bulk intrinsic type amorphous silicon layer is formed by delivering a silane containing gas and a hydrogen containing gas at a hydrogen to silane gas ratio of less than about 20;

1.