Memory devices with enhanced isolation of memory cells, systems including same and methods of forming same

• US 8,203,134 B2
• Filed: 09/21/2009
• Issued: 06/19/2012
• Est. Priority Date: 09/21/2009
• Status: Active Grant

• Current Assignee: Ovonyx Memory Technology, LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Liu, Jun
• Primary Examiner(s): Pert, Evan
• Assistant Examiner(s): Rodela, Eduardo A
• Application Number:
  US12/563,277
• Publication Number:
  US 20110068313A1
• Time in Patent Office: 1,002 Days
• Field of Search: 257/1, 257/2, 257/3, 257/4, 257/5, 257/52, 257/64, 257/65, 257/536, 257/577, 257/E27.025, 257/E27.047, 257/E27.101, 365/148
• US Class Current: 257/4
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8418 adapted for focusing electric field or current, e.g. tip-shaped
• CPC Class Codes: H10N 70/8616 Thermal insulation means
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

Memory cells of a memory device including a variable resistance material have a cavity between the memory cells. Electronic systems include such memory devices. Methods of forming a memory device include providing a cavity between memory cells of the memory device.

Claims

1. A memory device comprising:

at least a first memory cell and a second memory cell on a substrate, each memory cell comprising;

a first electrode;

a second electrode; and

a volume of variable resistance material between the first electrode and the second electrode;

a cavity disposed between the at least a first memory cell and the second memory cell;

a dielectric material extending over and between the at least a first memory cell and the second memory cell on a side thereof opposite the substrate, the dielectric material at least partially defining a boundary of the cavity; and

a passivation material over at least a portion of the volume of variable resistance material of each of the at least a first memory cell and the second memory cell, the passivation material partially defining the boundary of the cavity, wherein the cavity extends from a portion of the passivation material over the at least a portion of the volume of variable resistance material of the at least a first memory cell to a portion of the passivation material over the at least a portion of the volume of variable resistance material of the second memory cell.

2. The memory device of claim 1, wherein the dielectric material comprises a non-conformal dielectric material.

3. The memory device of claim 2, wherein the non-conformal dielectric material is disposed on a portion of the passivation material.

4. The memory device of claim 2, wherein a portion of the at least a first memory cell, a portion of the second memory cell, and a portion of the non-conformal dielectric material at least partially enclose the cavity.

5. The memory device of claim 4, wherein the enclosed cavity comprises a vacuum.

6. The memory device of claim 1, wherein the first electrode and the second electrode each comprise a discrete volume of conductive material.

7. The memory device of claim 1, wherein the volume of variable resistance material comprises a phase change material.

8. The memory device of claim 1, further comprising a second dielectric material surrounding a portion of the volume of variable resistance material of each of the at least a first memory cell and the second memory cell.

9. A memory device comprising:

at least a first memory cell and a second memory cell on a substrate, each memory cell comprising;

a first electrode;

a second electrode; and

a volume of variable resistance material between the first electrode and the second electrode;

a cavity disposed between the at least a first memory cell and the second memory cell; and

a dielectric material extending over and between the at least a first memory cell and the second memory cell on a side thereof opposite the substrate, the dielectric material at least partially defining a boundary of the cavity, wherein the first electrode and the second electrode of each of the at least a first memory cell and the second memory cell are disposed on a side of the volume of variable resistance material proximate the substrate.

10. The memory device of claim 9, wherein each of the at least a first memory cell and the second memory cell comprises:

at least two discrete conductive material structures disposed on a side of the volume of variable resistance material opposite the substrate; and

a second dielectric material disposed on and extending between the at least two discrete conductive material structures.

11. A memory device comprising:

a vacuum cavity disposed between a volume of variable resistance material of a first memory cell and a volume of variable resistance material of a second memory cell;

a non-conformal dielectric material extending over and between an end of each of the first memory cell and the second memory cell, the vacuum cavity at least partially bounded by the non-conformal dielectric material; and

a dielectric material surrounding the volume of variable resistance material of the first memory cell and the volume of variable resistance material of the second memory cell, wherein at least a portion of the vacuum cavity extends from the dielectric material surrounding the volume of variable resistance material of the first memory cell to the dielectric material surrounding the volume of variable resistance material of the second memory cell.

12. The memory device of claim 11, wherein a first portion of the vacuum cavity is disposed directly between the volume of variable resistance material of the first memory cell and the volume of variable resistance material of the second memory cell, and a second portion of the vacuum cavity is disposed directly between an electrode of the first memory cell and an electrode of the second memory cell.

13. A memory device comprising:

a substrate;

a plurality of memory cells, at least two adjacent memory cells of the plurality each comprising;

a first electrode disposed over the substrate;

a second electrode; and

a volume of variable resistance material disposed between the first electrode and the second electrode;

a non-conformal dielectric material extending over and between a distal end of each of the at least two adjacent memory cells;

a vacuum cavity disposed between the at least two adjacent memory cells and between the substrate and the non-conformal dielectric material; and

a dielectric material surrounding the first electrode of each of the at least two adjacent memory cells of the plurality of memory cells, wherein the vacuum cavity extends from the dielectric material surrounding the first electrode of one memory cell of the at least two adjacent memory cells to the dielectric material surrounding the first electrode of another memory cell of the at least two adjacent memory cells of the plurality of memory cells.

14. The memory device of claim 13, further comprising another dielectric material surrounding the volume of variable resistance material of each of the at least two adjacent memory cells of the plurality of memory cells.

15. The memory device of claim 14, wherein the vacuum cavity extends from the another dielectric material surrounding the volume of variable resistance material of one memory cell of the at least two adjacent memory cells of the plurality of memory cells to the another dielectric material surrounding the volume of variable resistance material of another memory cell of the at least two adjacent memory cells of the plurality of memory cells.

16. An electronic system comprising:

at least one electronic signal processor;

at least one memory device configured to communicate electrically with the at least one electronic signal processor, the at least one memory device comprising;

a plurality of memory cells, each memory cell of the plurality comprising;

a first electrode;

a second electrode; and

a volume of variable resistance material disposed between the first electrode and the second electrode; and

a vacuum cavity disposed between the volume of variable resistance material of a first memory cell of the plurality of memory cells and the volume of variable resistance material of a second memory cell of the plurality of memory cells;

a dielectric material surrounding a portion of the volume of variable resistance material of each memory cell of the plurality of memory cells, wherein the vacuum cavity extends from the dielectric material surrounding the portion of the volume of variable resistance material of a first memory cell of the plurality of memory cells to the dielectric material surrounding the portion of the volume of variable resistance material of a second memory cell of the plurality of memory cells; and

at least one of an input device and an output device configured to communicate electrically with the at least one electronic signal processor.