Memory device and semiconductor device

• US 8,203,142 B2
• Filed: 12/23/2010
• Issued: 06/19/2012
• Est. Priority Date: 04/28/2006
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Tokunaga, Hajime, Kato, Kiyoshi
• Primary Examiner(s): Dang, Phuc
• Application Number:
  US12/977,836
• Publication Number:
  US 20110089475A1
• Time in Patent Office: 544 Days
• Field of Search: 257/40, 257/296, 257/E27.084
• US Class Current: 257/40
• CPC Class Codes: H01L 27/13 combined with thin-film or thick-film passive components

Abstract

A memory device capable of data writing at a time other than during manufacturing is provided by using a memory element including an organic material. In a memory cell, a third conductive film, an organic compound, and a fourth conductive film are stacked over a semiconductor film provided with an n-type impurity region and a p-type impurity region, and a pn-junction diode is serially connected to the memory element. A logic circuit for controlling the memory cell includes a thin film transistor. The memory cell and the logic circuit are manufactured over one substrate at the same time. The n-type impurity region and the p-type impurity region of the memory cell are manufactured at the same time as the impurity region of the thin film transistor.

Claims

1. A memory device comprising:

a transistor comprising a first impurity region, a second impurity region, and a channel forming region between the first impurity region and the second impurity region, wherein each of the first impurity region and the second impurity region has one of an n-type conductivity and a p-type conductivity and includes a first impurity for imparting the one of the n-type conductivity or the p-type conductivity;

a diode comprising an n-type impurity region and a p-type impurity region being in direct contact with the n-type impurity region;

a memory element electrically connected to a first terminal of the diode; and

a wiring electrically connected to a second terminal of the diode;

wherein the n-type impurity region or the p-type impurity region of the diode includes a second impurity for imparting the same conductivity as that of the first impurity, and

wherein a concentration of the first impurity included in at least one of the first impurity region and the second impurity region is the same or substantially same as a concentration of the second impurity included in the one of the n-type impurity region and the p-type impurity region of the diode.

2. The memory device according to claim 1, wherein the transistor comprises a semiconductor film including the first impurity region, the second impurity region, and the channel forming region.

3. The memory device according to claim 1, wherein the diode comprises a semiconductor film including the n-type impurity region and the p-type impurity region.

4. The memory device according to claim 1,

wherein the transistor comprises a first semiconductor film including the first impurity region, the second impurity region, and the channel forming region,

wherein the diode comprises a second semiconductor film including the n-type impurity region and the p-type impurity region, and

wherein the first semiconductor film and the second semiconductor film are provided over the same insulating surface.

5. The memory device according to claim 4, wherein the first semiconductor film and the second semiconductor film are provided in direct contact with the same insulating surface.

6. The memory device according to claim 1, wherein the memory element comprises:

a first electrode layer electrically connected to one of the n-type impurity region and the p-type impurity region;

an organic compound layer over the first electrode layer; and

a second electrode layer over the organic compound layer.

7. The memory device according to claim 1, wherein the memory element is provided over the diode.

8. The memory device according to claim 1, wherein the n-type impurity region and the p-type impurity region is provided on the same insulating surface.

9. A memory device comprising:

a transistor comprising a first impurity region, a second impurity region, and a channel forming region between the first impurity region and the second impurity region;

a diode comprising an n-type impurity region and a p-type impurity region being in direct contact with the n-type impurity region;

a memory element electrically connected to one of the n-type impurity region and the p-type impurity region; and

a wiring electrically connected to the other of the n-type impurity region and the p-type impurity region;

wherein the first impurity region and the second impurity region comprise an impurity imparting one conductive type to the first impurity region and the second impurity region, and

wherein a concentration of the impurity is different from that of one of the n-type impurity region and the p-type impurity region.

10. The memory device according to claim 9, wherein the transistor comprises a semiconductor film including the first impurity region, the second impurity region, and the channel forming region.

11. The memory device according to claim 9, wherein the diode comprises a semiconductor film including the n-type impurity region and the p-type impurity region.

12. The memory device according to claim 9,

wherein the transistor comprises a first semiconductor film including the first impurity region, the second impurity region, and the channel forming region,

wherein the diode comprises a second semiconductor film including the n-type impurity region and the p-type impurity region, and

wherein the first semiconductor film and the second semiconductor film are provided over the same insulating surface.

13. The memory device according to claim 12, wherein the first semiconductor film and the second semiconductor film are provided in direct contact with the same insulating surface.

14. The memory device according to claim 9, wherein the memory element comprises:

a first electrode layer electrically connected to one of the n-type impurity region and the p-type impurity region;

an organic compound layer over the first electrode layer; and

a second electrode layer over the organic compound layer.

15. The memory device according to claim 9, wherein the memory element is provided over the diode.

16. The memory device according to claim 9, wherein the n-type impurity region and the p-type impurity region is provided on the same insulating surface.

17. A memory device comprising:

a thin film transistor comprising a first semiconductor film including a first impurity region, a second impurity region, and a channel forming region between the first impurity region and the second impurity region;

a diode comprising a second semiconductor film including an n-type impurity region and a p-type impurity region being in direct contact with the n-type impurity region;

a memory element electrically connected to one of the n-type impurity region and the p-type impurity region; and

a wiring electrically connected to the other of the n-type impurity region and the p-type impurity region;

wherein the first semiconductor film and the second semiconductor film are provided over the same insulating surface.

18. The memory device according to claim 17, wherein the first semiconductor film and the second semiconductor film are provided in direct contact with the same insulating surface.

19. The memory device according to claim 17, wherein the memory element comprises:

a first electrode layer electrically connected to one of the n-type impurity region and the p-type impurity region;

an organic compound layer over the first electrode layer; and

a second electrode layer over the organic compound layer.

20. The memory device according to claim 17, wherein the memory element is provided over the diode.

21. The memory device according to claim 17, wherein the n-type impurity region and the p-type impurity region is provided on the same insulating surface.

22. A semiconductor device comprising:

a memory portion comprising;

a transistor comprising a first impurity region, a second impurity region, and a channel forming region between the first impurity region and the second impurity region, wherein each of the first impurity region and the second impurity region has one of an n-type conductivity and a p-type conductivity and includes a first impurity for imparting the one of the n-type conductivity or the p-type conductivity;

a diode comprising an n-type impurity region and a p-type impurity region being in direct contact with the n-type impurity region;

a memory element electrically connected to one of the n-type impurity region and the p-type impurity region;

a wiring electrically connected to the other of the n-type impurity region and the p-type impurity region; and

an antenna functionally connected to the memory portion through a controlling circuit,

wherein the n-type impurity region or the p-type impurity region of the diode includes a second impurity for imparting the same conductivity as that of the first impurity, and

wherein a concentration of the first impurity comprised in at least one of the first impurity region and the second impurity region is the same or substantially same as a concentration of the second impurity in the one of the n-type impurity region and the p-type impurity region of the diode.

23. The semiconductor device according to claim 22, wherein the transistor comprises a semiconductor film including the first impurity region, the second impurity region, and the channel forming region.

24. The semiconductor device according to claim 22, wherein the diode comprises a semiconductor film including the n-type impurity region and the p-type impurity region.

25. The semiconductor device according to claim 22,

wherein the transistor comprises a first semiconductor film including the first impurity region, the second impurity region, and the channel forming region,

wherein the diode comprises a second semiconductor film including the n-type impurity region and the p-type impurity region, and

wherein the first semiconductor film and the second semiconductor film are provided over the same insulating surface.

26. The semiconductor device according to claim 25, wherein the first semiconductor film and the second semiconductor film are provided in direct contact with the same insulating surface.

27. The semiconductor device according to claim 22, wherein the memory element comprises:

a first electrode layer electrically connected to one of the n-type impurity region and the p-type impurity region;

an organic compound layer over the first electrode layer; and

a second electrode layer over the organic compound layer.

28. The semiconductor device according to claim 22, wherein the memory element is provided over the diode.

29. The semiconductor device according to claim 22, wherein the semiconductor device is one selected from the group consisting of an RFID tag, an ID tag, an IC tag, an IC chip, an RF tag, a wireless tag, an electronic tag, and a wireless chip.

30. The semiconductor device according to claim 22, wherein the n-type impurity region and the p-type impurity region is provided on the same insulating surface.

31. A semiconductor device comprising:

a memory portion comprising;

a transistor comprising a first impurity region, a second impurity region, and a channel forming region between the first impurity region and the second impurity region;

a diode comprising an n-type impurity region and a p-type impurity region being in direct contact with the n-type impurity region;

a memory element electrically connected to one of the n-type impurity region and the p-type impurity region;

a wiring electrically connected to the other of the n-type impurity region and the p-type impurity region; and

an antenna functionally connected to the memory portion through a controlling circuit,

wherein the first impurity region and the second impurity region comprise an impurity imparting one conductive type to the first impurity region and the second impurity region, and

wherein a concentration of the impurity is same or substantially same as that of one of the n-type impurity region and the p-type impurity region.

32. The semiconductor device according to claim 31, wherein the transistor comprises a semiconductor film including the first impurity region, the second impurity region, and the channel forming region.

33. The semiconductor device according to claim 31, wherein the diode comprises a semiconductor film including the n-type impurity region and the p-type impurity region.

34. The semiconductor device according to claim 31,

wherein the transistor comprises a first semiconductor film including the first impurity region, the second impurity region, and the channel forming region,

wherein the diode comprises a second semiconductor film including the n-type impurity region and the p-type impurity region, and

wherein the first semiconductor film and the second semiconductor film are provided over the same insulating surface.

35. The semiconductor device according to claim 34, wherein the first semiconductor film and the second semiconductor film are provided in direct contact with the same insulating surface.

36. The semiconductor device according to claim 31, wherein the memory element comprises:

a first electrode layer electrically connected to one of the n-type impurity region and the p-type impurity region;

an organic compound layer over the first electrode layer; and

a second electrode layer over the organic compound layer.

37. The semiconductor device according to claim 31, wherein the memory element is provided over the diode.

38. The semiconductor device according to claim 31, wherein the semiconductor device is one selected from the group consisting of an RFID tag, an ID tag, an IC tag, an IC chip, an RF tag, a wireless tag, an electronic tag, and a wireless chip.

39. The semiconductor device according to claim 31, wherein the n-type impurity region and the p-type impurity region is provided on the same insulating surface.

40. A semiconductor device comprising:

a memory portion comprising;

a thin film transistor comprising a first semiconductor film including a first impurity region, a second impurity region, and a channel forming region between the first impurity region and the second impurity region;

a diode comprising a second semiconductor film including an n-type impurity region and a p-type impurity region being in direct contact with the n-type impurity region;

a memory element electrically connected to one of the n-type impurity region and the p-type impurity region; and

a wiring electrically connected to the other of the n-type impurity region and the p-type impurity region; and

an antenna functionally connected to the memory portion through a controlling circuit,

wherein the first semiconductor film and the second semiconductor film are provided over the same insulating surface.

41. The semiconductor device according to claim 40, wherein the first semiconductor film and the second semiconductor film are provided in direct contact with the same insulating surface.

42. The semiconductor device according to claim 40, wherein the memory element comprises:

a first electrode layer electrically connected to one of the n-type impurity region and the p-type impurity region;

an organic compound layer over the first electrode layer; and

a second electrode layer over the organic compound layer.

43. The semiconductor device according to claim 40, wherein the memory element is provided over the diode.

44. The semiconductor device according to claim 40, wherein the semiconductor device is one selected from the group consisting of an RFID tag, an ID tag, an IC tag, an IC chip, an RF tag, a wireless tag, an electronic tag, and a wireless chip.

45. The semiconductor device according to claim 40, wherein the n-type impurity region and the p-type impurity region is provided on the same insulating surface.