Integrated circuits utilizing amorphous oxides

• US 8,203,146 B2
• Filed: 09/15/2010
• Issued: 06/19/2012
• Est. Priority Date: 11/10/2004
• Status: Active Grant

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.), Japan Science & Technology Trading Co. Limited, Tokyo Institute of Technology (National University Corporation Tokyo Institute of Technology)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.), Tokyo Institute of Technology (National University Corporation Tokyo Institute of Technology)
• Inventors: Abe, Katsumi, Hosono, Hideo, Kamiya, Toshio, Nomura, Kenji
• Primary Examiner(s): Yang, Minchul
• Application Number:
  US12/882,404
• Publication Number:
  US 20110024741A1
• Time in Patent Office: 643 Days
• Field of Search: 257/58, 257/59, 257/62, 257/72, 257/52, 257/E29.083, 257/E29.092, 257/E29.101
• US Class Current: 257/58
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Semiconductor devices and circuits with use of transparent oxide film are provided. The semiconductor device having a P-type region and an N-type region, wherein amorphous oxides with electron carrier concentration less than 10¹⁸/cm³ is used for the N-type region.

Claims

1. An integrated circuit comprising a P-type TFT and an N-type TFT,

wherein the N-type TFT comprises an amorphous oxide of a compound having

(a) a composition when in crystalline state represented by In₂₋

xM3_xO₃ (Zn<sub>1−

y</sub>M2_yO)_m, wherein M2 is Mg or Ca;

M3 is B, Al, Ga or Y;

0≦

x≦

2;

0≦

y≦

1; and

m is zero or a natural number less than 6, or a mixture of said compounds;

(b) an electron carrier concentration of greater than 10¹²/cm³; and

(c) oxygen defect density decreased by treatment in an atmosphere including oxygen at a predetermined pressure during or after formation of a film of the amorphous oxide.

2. The integrated circuit according to claim 1, wherein said amorphous oxide contains at least one of In, Zn, and Sn.

3. The integrated circuit according to claim 1, wherein said amorphous oxide is at least an oxide containing In, Zn, and Sn, an oxide containing In and Zn, oxides containing In and Sn, and an oxide containing In.

4. The integrated circuit according to claim 1, wherein said amorphous oxide is an oxide containing In, Ga, and Zn.

5. The integrated circuit according to claim 1, wherein a P-type semiconductor having an absolute value of Fermi level being larger than an absolute value of Fermi level of said amorphous oxide in said N-type TFT is used as a material in said P-type TFT.

11. The integrated circuit according to any one of claims 1 and 9, wherein the amorphous oxide contains a group-IV element M4, wherein M4 is selected from the group consisting of Sn, Si, Ge, and Zr.

6. An integrated circuit, comprising a circuit, which includes an N-type TFT using amorphous oxide of a compound having

(a) a composition when in crystalline state represented by In₂₋

xM3_xO₃(Zn<sub>1−

y</sub>M2_yO)_m, wherein M2 is Mg or Ca;

M3 is B, Al, Ga or Y;

0≦

x≦

2;

0≦

y≦

1; and

m is zero or a natural number less than 6, or a mixture of said compounds;

(b) an electron carrier concentration of greater than 10¹²/cm³ and less than 10¹⁸/cm³, wherein an N-type semiconductor has less than 10 micro-ampere of current between drain and source terminals when no gate voltage is applied; and

(c) oxygen defect density decreased by treatment in an atmosphere including oxygen at a predetermined pressure during or after formation of a film of the amorphous oxide.

7. The integrated circuit according to claim 6, wherein the N-type TFT is used in at least any of a logic circuit, a memory circuit, and a differential amplifier circuit.

8. The integrated circuit of claim 6 when the amorphous oxide contains a group IV element M4, wherein M4 is selected from the group consisting of Sn, Si, Ge, and Zr.

9. An integrated circuit comprising a first region, a second region and an N-type TFT, the first region and the second region form a heterojunction, and the first region and an active layer of the N-type TFT contain an amorphous oxide satisfying the following conditions (a), (b), and (c)

(a) a composition when in crystalline state represented by In₂₋

xM3_xO₃(Zn<sub>1−

y</sub>M2_yO)_m, wherein M2 is Mg or Ca;

M3 is B, Al, Ga or Y;

0≦

x≦

2;

0≦

y≦

1; and

m is zero or a natural number less than 6, or a mixture of said compounds;

(b) an electron carrier concentration of greater than 10¹²/cm³ and less than 10¹⁸/cm³; and

(c) oxygen defect density decreased by treatment in an atmosphere including oxygen at a predetermined pressure during or after formation of a film of the amorphous oxide.

10. The integrated circuit according to claim 9, wherein said amorphous oxide is at least an oxide containing In, Zn, and Sn, an oxide containing In and Zn, an oxide containing In and Sn, and an oxide containing In.

12. An integrated circuit comprising a P-type region and an N-type region, wherein the N-type region comprises an N-type TFT comprising an amorphous oxide of a compound having

(a) the amorphous oxides are any of oxides containing In, Ga and Zn, oxides containing In, Zn, and Sn, oxides containing In and Zn, oxides containing In and Sn, and oxides containing In;

(b) an electron carrier concentration of greater than 10¹²/cm³ and less than 10¹⁸/cm³, wherein an electron mobility of the amorphous oxide increases when the electron carrier concentration increases; and

(c) oxygen defect density decreased by treatment in an atmosphere including oxygen at a predetermined pressure during or after formation of a film of the amorphous oxide.

13. An integrated circuit, comprising a circuit, which includes an N-type TFT using amorphous oxide of a compound having

(a) the amorphous oxides are any of oxides containing In, Ga and Zn, oxides containing In, Zn, and Sn, oxides containing In and Zn, oxides containing In and Sn, and oxides containing In;

(b) an electron carrier concentration of greater than 10¹²/cm³ and less than 10¹⁸/cm³, wherein an electron mobility of the amorphous oxide increases when the electron carrier concentration increases as an N-type semiconductor and which has less than 10 micro-ampere of current between drain and source terminals when no gate voltage is applied; and

(c) oxygen defect density decreased by treatment in an atmosphere including oxygen at a predetermined pressure during or after formation of a film of the amorphous oxide.

14. An integrated circuit comprising a first region, a second region and an N-type TFT, the first region and the second region form a heterojunction, and the first region and an active layer of the N-type TFT contain an amorphous oxide satisfying the following conditions (a), (b) and (c)

(a) the amorphous oxides are any of oxides containing In, Ga, and Zn, oxides containing In, Zn and Sn, oxides containing In and Zn, oxides containing In and Sn, and oxides containing In;

(b) an electron carrier concentration of greater than 10¹²/cm³ and less than 10¹⁸/cm³, wherein an electron mobility of the amorphous oxide increases when the electron carrier concentration increases, and a second region forming a heterojunction to said first region; and

(c) oxygen defect density decreased by treatment in an atmosphere including oxygen at a predetermined pressure during or after formation of a film of the amorphous oxide.