Semiconductor device and structure

• US 8,203,148 B2
• Filed: 06/30/2011
• Issued: 06/19/2012
• Est. Priority Date: 10/11/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Sekar, Deepak C., Or-Bach, Zvi
• Primary Examiner(s): Kebede, Brook
• Application Number:
  US13/173,999
• Publication Number:
  US 20120086067A1
• Time in Patent Office: 355 Days
• Field of Search: 438149-167, 438238-240, 438257-267, 438386-396, 257 67- 71, 257/304, 257/308, 257/312, 257/905, 257/E27.084
• US Class Current: 257/67
• CPC Class Codes: H01L 2029/7857 of the accumulation type
• CPC Class Codes: H01L 21/268 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2221/6835 used as a support during build up manufacturing of active devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/36 the transistor being a FinFET
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/41 : of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 61/22 : of the field-effect transistor [FET] type
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/84 : arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10B 63/845 : the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/20 : Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/823 : adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8833 : Binary metal oxides, e.g. TaOx

Abstract

A device, comprising: a first layer and a second layer wherein both said first layer and said second layer are mono-crystalline, wherein said first layer comprises first transistors, wherein said second layer comprises second transistors, wherein at least one of said second transistors substantially overlays one of said first transistors, and wherein both said first transistors and said second transistors are processed following the same lithography step.

Claims

1. A device, comprising:

a first layer and a second layer wherein both said first layer and said second layer are mono-crystalline,

wherein said first layer comprises first transistors,

wherein said second layer comprises second transistors,

wherein at least one of said second transistors substantially overlays one of said first transistors, and

wherein both said first transistors and said second transistors are processed following the same lithography step.

2. A device according to claim 1, further comprising:

a plurality of memory cell control lines wherein said control lines comprise a portion of said first layer or said second layer.

3. A device according to claim 1, wherein said first transistors and said second transistors comprise side gates.

4. A device according to claim 1, wherein said device further comprises a dynamic random access memory (DRAM).

5. A device according to claim 1, wherein said device further comprises a charge-trap type memory.

6. A device according to claim 1, wherein said device further comprises a floating-gate type memory.

7. A device according to claim 1, wherein said device further comprises a resistive-random-access memory (RRAM).

8. A device according to claim 1, wherein said device further comprises a phase-change type memory.

9. A device, comprising:

a first layer and a second layer wherein both said first layer and said second layer are mono-crystalline,

wherein said first layer comprises first transistors and said second layer comprises second transistors,

wherein said device further comprises first select lines as memory cell control lines,

wherein said first select lines comprise a portion of said first layer,

wherein said device further comprises second select lines as memory cell control lines, and

wherein said second select lines comprise a portion of said second layer.

10. A device according to claim 9, wherein at least one of said second transistors substantially overlays one of said first transistors, wherein both the at least one of said second transistors and said one of said first transistors are processed following the same lithography step.

11. A device according to claim 9, wherein said first transistors and said second transistors comprise side gates.

12. A device according to claim 9, wherein said device further comprises a DRAM type memory.

13. A device according to claim 9 wherein said device further comprises a resistive-RAM type memory.

14. A device according to claim 9, wherein said device further comprises a floating-gate type memory.

15. A device, comprising:

a first mono-crystalline layer and a second mono-crystalline layer,

wherein said first layer comprises first transistors,

wherein said second layer comprises second transistors,

wherein said first transistors and said second transistors are horizontally oriented transistors, and

wherein said first transistors and said second transistors comprise side gates.

16. A device according to claim 15, further comprising:

a plurality of memory cell control lines embedded within said first layer and said second layer.

17. A device according to claim 15, wherein at least one of said second transistors substantially overlays one of said first transistors, and wherein both said second transistors and said one of said first transistors are processed following the same lithography step.

18. A device according to claim 15, wherein said device further comprises a DRAM type memory.

19. A device according to claim 15, wherein said device further comprises a resistive-RAM type memory.

20. A device according to claim 15, wherein said device comprises a floating-gate type memory.

21. A device according to claim 15 wherein said device further comprises a phase-change type memory.

22. A device according to claim 15, wherein said device further comprises a charge-trap type memory.

23. A device according to claim 15, wherein said second layer is transferred using an ion-cut layer transfer process.