×

3D memory array arranged for FN tunneling program and erase

  • US 8,203,187 B2
  • Filed: 02/12/2010
  • Issued: 06/19/2012
  • Est. Priority Date: 03/03/2009
  • Status: Active Grant
First Claim
Patent Images

1. A 3D array of memory cells, comprising:

  • a plurality of two-cell structures arranged in three dimensions, the two cell structures including a semiconductor body pillar, first and second bit line pillars on opposing first and second sides of the semiconductor body pillar, dielectric charge trapping structures on third and fourth opposing sides of the semiconductor body pillar, a first word line arranged adjacent the dielectric charge trapping structure on the third side of the semiconductor body pillar and a second word line arranged adjacent the dielectric charge trapping structure on the fourth side of the semiconductor body pillar; and

    a controller arranged to program and erase selected memory cells in the plurality of two-cell structures by biasing corresponding semiconductor body pillars and one of the first or second word lines to induce Fowler-Nordheim tunneling.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×