3D memory array arranged for FN tunneling program and erase

• US 8,203,187 B2
• Filed: 02/12/2010
• Issued: 06/19/2012
• Est. Priority Date: 03/03/2009
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lung, Hsiang-Lan, Shih, Yen-Hao, Lai, Erh-Kun, Lee, Ming Hsiu, Lue, Hang-Ting
• Primary Examiner(s): Pham, Long
• Application Number:
  US12/705,158
• Publication Number:
  US 20100265773A1
• Time in Patent Office: 858 Days
• Field of Search: 257/197, 257/390, 257/E21.54, 438/197, 438/257, 365/185.25, 365/185.28
• US Class Current: 257/390
• CPC Class Codes: G11C 16/0458 comprising two or more independent floating gates which store independent data
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.

Claims

1. A 3D array of memory cells, comprising:

a plurality of two-cell structures arranged in three dimensions, the two cell structures including a semiconductor body pillar, first and second bit line pillars on opposing first and second sides of the semiconductor body pillar, dielectric charge trapping structures on third and fourth opposing sides of the semiconductor body pillar, a first word line arranged adjacent the dielectric charge trapping structure on the third side of the semiconductor body pillar and a second word line arranged adjacent the dielectric charge trapping structure on the fourth side of the semiconductor body pillar; and

a controller arranged to program and erase selected memory cells in the plurality of two-cell structures by biasing corresponding semiconductor body pillars and one of the first or second word lines to induce Fowler-Nordheim tunneling.

2. The memory device of claim 1, wherein the charge trapping structures include a tunneling layer adjacent the corresponding first or second word line, a dielectric charge trapping layer, and a blocking layer adjacent the corresponding semiconductor body pillar, and said controller is arranged to induce Fowler-Nordheim tunneling of charge from the corresponding first or second word line through the tunneling layer.

3. The memory device of claim 1, including decoder circuitry, the decoder circuitry including

an array of access devices coupled to semiconductor body pillars and arranged to bias individual semiconductor body pillars;

a bottom bit line decoder coupled to the first bit line pillars arranged to access individual columns of first bit line pillars;

a top bit line decoder coupled to the second bit line pillars and arranged to access individual rows of bit line pillars; and

a fourth decoder coupled to the first and second word lines, and arranged to drive one of a first or a second word lines on selected levels in the plurality of two-cell structures.

4. The memory device of claim 1, arranged for random access AND-decoding.

5. The memory device of claim 1, wherein the first and second bit line pillars comprise semiconductor material with a core comprising a metal or metal silicide.

6. A 3D array of memory cells, comprising:

a plurality of structures arranged in three dimensions, the structures including a plurality of semiconductor body pillars, first and second bit line pillars on opposing first and second sides of the semiconductor body pillars, data storage structures on third sides of the semiconductor body pillars, and a word line arranged adjacent the data storage structures on the third sides of the semiconductor body pillars; and

a controller arranged to program and erase selected memory cells in the plurality of structures by biasing corresponding semiconductor body pillars to induce Fowler-Nordheim tunneling.

7. A memory device including a 3D array of memory cells, comprising:

an integrated circuit substrate;

an array of semiconductor body pillars and bit line pillars on the substrate arranged to intersect a plurality of word line levels including word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars, the semiconductor body pillars in the array having corresponding bit line pillars on opposing first and second sides, and having first and second channel surfaces on opposing third and fourth sides;

dielectric charge trapping structures on the first and second channel surfaces of the semiconductor body pillars in the array;

the word line structures in the plurality of levels respectively having a first set of word lines arranged adjacent the dielectric charge trapping structures on semiconductor body pillars in the array and a second set of word lines arranged adjacent the dielectric charge trapping structures on semiconductor body pillars in the array;

the bit line pillars in the array including bottom-decoded pillars on said first sides of the semiconductor body pillars and top-decoded pillars on said second sides of the semiconductor body pillars;

decoder circuitry coupled to the array of semiconductor body pillars and bit line pillars, to the levels of word line structures, arranged to access selected memory cells in the 3D array; and

a controller arranged to program and erase selected memory cells in the 3D array by biasing the corresponding semiconductor body pillars and one of the first or second sets of word lines in the corresponding level, and to read selected memory cells in the 3D array by sensing current in bit line pillars on opposing sides of corresponding semiconductor body pillars in response to gate voltages applied to one of the first or second sets of word lines in the corresponding level.

8. The memory device of claim 7, wherein the decoder circuitry includes

an array of access devices coupled to the semiconductor body pillars in the array arranged to bias individual semiconductor body pillars;

a bottom bit line decoder coupled to the bit line pillars on the first sides of the semiconductor body pillars in the array arranged to access individual columns of bit line pillars;

a top bit line decoder coupled to the bit line pillars on the second sides of the semiconductor body pillars in the array arranged to access individual rows of bit line pillars; and

a fourth decoder coupled to the word line structures in the plurality of word line levels, and arranged to drive one of a first set or a second set of word lines on selected word line levels.

9. The memory device of claim 7, including control circuits to bias selected memory cells in the 3D array for gate injection Fowler-Nordheim programming.

10. The memory device of claim 7, including control circuits to bias selected memory cells in the 3D array for gate injection Fowler-Nordheim electron tunneling programming and gate injection Fowler-Nordheim hole tunneling erasing operations.

11. The memory device of claim 7, wherein the array of semiconductor body pillars and bit line pillars is arranged in a pattern including unit sets of pillars, a unit set of pillars comprising a first bit line pillar, a semiconductor body pillar adjacent the first bit line pillar, a second bit line pillar adjacent the semiconductor body pillar, and an insulating member, whereby adjacent unit sets of pillars are insulated from each other by the insulating member.

12. The memory device of claim 7, wherein the bit line pillars in the array comprise semiconductor material with a core comprising a metal or metal silicide.

13. The memory device of claim 7, wherein the semiconductor body pillars in the array comprise p-type silicon and the bit line pillars in the array comprise n-type silicon.

14. The memory device of claim 7, wherein the dielectric charge trapping structure in a particular memory cell in the 3D array includes a tunneling layer, a charge trapping layer and a blocking layer between the semiconductor body pillar and the word line in a corresponding one of the first or second sets of word lines in a corresponding level.

15. The memory device of claim 7, arranged for random access AND-decoding.

16. A method for manufacturing a memory device, comprising:

forming a plurality of two-cell structures arranged in three dimensions, the two cell structures including a semiconductor body pillar, first and second bit line pillars on opposing first and second sides of the semiconductor body pillar, dielectric charge trapping structures on third and fourth opposing sides of the semiconductor body pillar, a first word line arranged adjacent the dielectric charge trapping structure on the third side of the semiconductor body pillar and a second word line arranged adjacent the dielectric charge trapping structure on the fourth side of the semiconductor body pillar;

said just mentioned forming including;

providing a substrate including an array of access devices and a first set of bit lines, the substrate having a surface with an array of contacts, including contacts coupled to access devices in the array of access devices and contacts coupled to bit lines in the set of bit lines;

forming a stack of alternating layers of word line material and insulating material over the array of contacts;

forming trenches in the stack, the trenches exposing respective rows of contacts on the surface of the substrate coupled to access devices and exposing contacts on the surface of the substrate coupled to bit lines in the first set of bit lines, and having sidewalls exposing word line material in the layers of word line material in the stack;

forming a charge trapping structure, lining the sidewalls of the trenches at least on word line material exposed on sidewalls of the trenches;

forming semiconductor body pillars within the trenches over the charge trapping structure, the semiconductor body pillars contacting respective contacts in the rows of contacts in the trenches;

forming bit line pillars within the trenches on first and second opposing sides of the semiconductor body pillars and within the trenches, where bit line pillars on the first side of the semiconductor body pillars contact respective contacts coupled to a bit line in the first set of bit lines; and

forming a second set of bit lines coupled to the bit line pillars on the second opposing side of the semiconductor body pillars; and

forming a controller arranged to program and erase selected memory cells in the plurality of two-cell structures by biasing corresponding semiconductor body pillars and one of the first or second word lines to induce Fowler-Nordheim tunneling.

17. The method of claim 16, wherein said forming semiconductor body pillars includes filling the trenches with doped semiconductor material over the charge trapping structure, and then applying a patterned etch process to remove the doped semiconductor material within the trenches to leave said semiconductor body pillars.

18. The method of claim 17, wherein said forming bit line pillars includes filling regions left by said patterned etch process with bit line material to provide said bit line pillars.

19. The method of claim 16, wherein said forming bit line pillars includes providing a semiconductor pillar having a metal or metal silicide core as said bit line pillars.

20. The method of claim 16, wherein said forming a charge trapping structure includes forming a multilayer stack of dielectric materials on the sidewalls of the trenches, the multilayer stack including a tunneling layer, a charge trapping layer and a blocking layer.

21. The method of claim 16, wherein said tunneling layer is formed adjacent the sidewalls of the trenches.

22. The method of claim 16, wherein said forming trenches includes using a first lithographic mask to define a pattern for the trenches, and said forming semiconductor body pillars includes using a second lithographic mask to define a pattern for the semiconductor body pillars in the trenches.

23. The method of claim 16, including etching the stack to define left side word line structures including a plurality of word lines between alternating pairs of trenches, and right side word line structures including a second plurality of word lines interleaved with the first plurality of word lines between alternating pairs of trenches.

24. The method of claim 16, including forming insulating pillars in the trenches, between bit line pillars on the second opposing side of a first semiconductor body pillar and a bit line pillar of the first opposing side of a second semiconductor body pillar.