Integrated circuit package in package system with adhesiveless package attach

• US 8,203,214 B2
• Filed: 06/27/2007
• Issued: 06/19/2012
• Est. Priority Date: 06/27/2007
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac BVI limited (JCET Group Co., Ltd.)
• Inventors: Bathan, Henry Descalzo, Camacho, Zigmund Ramirez, Tay, Lionel Chien Hui, Punzalan, Jeffrey D.
• Primary Examiner(s): CHU, CHRIS C
• Application Number:
  US11/769,691
• Publication Number:
  US 20090001563A1
• Time in Patent Office: 1,819 Days
• Field of Search: 257/E21.505, 257/E23.01, 257/723, 257/724, 257/777, 257684-686, 257/690, 257/700, 257/E25.013, 257/E25.018, 257692-694, 257/666, 257/670, 257/672, 257/676, 438106-109, 438/111, 438/112, 361/760
• US Class Current: 257/777
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/49537 Plurality of lead frames mounted in one device
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 25/03 all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0781 : being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18165 : of a wire bonded chip
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

An integrated circuit package in package system includes a package in package lead with a package in package lead surface substantially planar, attaching a first integrated circuit package having a first encapsulant surface substantially coplanar with the package in package lead surface, attaching a second integrated circuit near the first integrated circuit package, and forming a package in package encapsulant over the first integrated circuit package and the second integrated circuit.

Claims

1. A method for manufacturing an integrated circuit package in package system comprising:

providing a package in package lead with a package in package lead surface substantially planar;

attaching a first integrated circuit package having a first package lead and a first encapsulant having a first encapsulant surface substantially coplanar with the package in package lead surface, the first package lead protruding from the first encapsulant;

attaching a second integrated circuit near the first integrated circuit package; and

forming a package in package encapsulant over the first integrated circuit package and the second integrated circuit, a side of the package in package lead opposite the package in package lead surface exposed from the package in package encapsulant.

2. The method as claimed in claim 1 wherein attaching the first integrated circuit package includes electrically connecting the first integrated circuit package to the package in package lead.

3. The method as claimed in claim 1 wherein attaching the second integrated circuit includes attaching the second integrated circuit over the first integrated circuit package.

4. The method as claimed in claim 1 wherein attaching the second integrated circuit includes attaching the second integrated circuit adjacent the first integrated circuit package.

5. The method as claimed in claim 1 wherein attaching the second integrated circuit includes attaching a second integrated circuit package having the second integrated circuit adjacent the first integrated circuit package.

6. A method for manufacturing an integrated circuit package in package system comprising:

forming a package in package lead having a package in package lead surface substantially planar to another package in package lead;

mounting a first integrated circuit package having a first package lead and a first encapsulant having a first encapsulant surface substantially coplanar with the package in package lead surface and another package in package lead surface, the first package lead protruding from the first encapsulant;

connecting a second integrated circuit to the first integrated circuit package with a second connector; and

applying a package in package encapsulant over the first integrated circuit package and the second integrated circuit, the package in package encapsulant having a plane of a package in package mounting surface substantially coplanar with the first encapsulant surface and the package in package lead surface, and a side of the package in package lead opposite the package in package lead surface exposed from the package in package encapsulant.

7. The method as claimed in claim 6 wherein connecting the second integrated circuit includes connecting the second integrated circuit having a second integrated circuit mounting surface substantially coplanar to the package in package mounting surface.

8. The method as claimed in claim 6 wherein connecting the second integrated circuit includes connecting the second integrated circuit over a die concealer adjacent the first integrated circuit package.

9. The method as claimed in claim 6 wherein forming the package in package lead includes forming the package in package lead in a shape of a J-bend lead.

10. The method as claimed in claim 6 wherein forming the package in package lead includes forming the package in package lead in a shape of a stackable lead having a top terminal and a bottom terminal.

11. An integrated circuit package in package system comprising:

a package in package lead with a package in package lead surface substantially planar;

a first integrated circuit package having a first package lead and a first encapsulant having a first encapsulant surface substantially coplanar with the package in package lead surface, the first package lead protruding from the first encapsulant;

a second integrated circuit near the first integrated circuit package; and

a package in package encapsulant over the first integrated circuit package and the second integrated circuit, a side of the package in package lead opposite the package in package lead surface exposed from the package in package encapsulant.

12. The system as claimed in claim 11 wherein the first integrated circuit package includes the first integrated circuit package electrically connected to the package in package lead.

13. The system as claimed in claim 11 wherein the second integrated circuit includes the second integrated circuit over the first integrated circuit package.

14. The system as claimed in claim 11 wherein the second integrated circuit includes the second integrated circuit adjacent the first integrated circuit package.

15. The system as claimed in claim 11 wherein the second integrated circuit includes a second integrated circuit package having the second integrated circuit adjacent the first integrated circuit package.

16. The system as claimed in claim 11 wherein:

the package in package lead with the package in package lead surface is substantially planar to another package in package lead;

the first integrated circuit package having a first encapsulant surface substantially coplanar with the package in package lead surface and another package in package lead surface;

the second integrated circuit is connected to the first integrated circuit package with a second connector; and

the package in package encapsulant is over the first integrated circuit package and the second integrated circuit, the package in package encapsulant having a plane of a package in package mounting surface substantially coplanar with the first encapsulant surface and the package in package lead surface.

17. The system as claimed in claim 16 wherein the second integrated circuit includes the second integrated circuit having a second integrated circuit mounting surface substantially coplanar to the package in package mounting surface.

18. The system as claimed in claim 16 wherein the second integrated circuit includes the second integrated circuit over a die concealer adjacent the first integrated circuit package.

19. The system as claimed in claim 16 wherein the package in package lead is in a shape of a J-bend lead.

20. The system as claimed in claim 16 wherein the package in package lead is in a shape of a stackable lead having a top terminal and a bottom terminal.