Frequency divider and method for frequency division

• US 8,203,367 B2
• Filed: 10/01/2008
• Issued: 06/19/2012
• Est. Priority Date: 10/16/2007
• Status: Active Grant

• Current Assignee: ams AG (Ams-Osram AG)
• Original Assignee: ams AG (Ams-Osram AG)
• Inventors: Leoncavallo, Ruggero
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Cole, Brandon s
• Application Number:
  US12/738,405
• Publication Number:
  US 20110044424A1
• Time in Patent Office: 1,357 Days
• Field of Search: 327/115, 327/116, 327/117, 327/118, 327355-360, 327/202, 327/203, 327208-212, 327/218, 377/47, 377/48
• US Class Current: 327/117
• CPC Class Codes: H03K 23/544 with a base which is an odd number

Abstract

A frequency divider and a method for frequency division are disclosed that can achieve a balanced duty cycle when performing a frequency division with an odd division ratio, independently of an input frequency.

Claims

1. A frequency divider, comprising:

a cascade of at least two triggered delay elements, each having a data input, a clock input, a trigger control input and a data output, the delay elements configured to forward a state of an input signal at their respective data input to their respective data output, wherein it depends on a control signal at the respective trigger control input of the delay element whether the state is forwarded either for a rising clock edge of a clock signal at their respective clock input or for a falling clock edge of the clock signal;

a reference frequency input; and

a clock output;

wherein the clock input of each of the delay elements of the cascade is coupled to the reference frequency input;

wherein the data input and the trigger control input of the first delay element of the cascade are coupled to the data output of the last delay element of the cascade;

wherein the data input and the trigger control input of further delay elements of the cascade are coupled to the data output of a respective preceding delay element of the cascade;

wherein the clock output is coupled to the data output of the last delay element of the cascade;

wherein the trigger control input of one of the delay elements of the cascade is coupled to the corresponding data output by inverting means; and

wherein the respective data input of the other delay elements of the cascade is coupled to the corresponding data output by respective inverting means.

2. The frequency divider according to claim 1, wherein at least one of the triggered delay elements comprises:

a selection unit having a first and a second signal input, a signal output, which is coupled to the data output of the at least one triggered delay element, and a selection input, which is coupled to the trigger control input of the at least one triggered delay element, the selection unit configured to couple the first or the second signal input to the signal output depending on a selection signal at the selection input; and

a first and a second auxiliary delay element each having an auxiliary data input, a clock input and an auxiliary data output, the auxiliary delay elements configured to forward a state of an input signal at their respective auxiliary data input to their respective auxiliary data output depending on a clock edge of a clock signal at their respective clock input;

wherein the auxiliary data inputs are coupled to the data input of the at least one triggered delay element;

wherein the auxiliary data outputs are coupled to the first and the second signal input;

wherein the clock input of the first auxiliary delay element is coupled to the clock input of the at least one triggered delay element; and

wherein the clock input of the second auxiliary delay element is coupled to the clock input of the at least one triggered delay element by auxiliary inverting means.

3. The frequency divider according to claim 1, which is configured to be operated with differential signals.

4. The frequency divider according to claim 3, wherein at least one of the inverting means comprises swapped differential lines.

5. The frequency divider according to claim 1, wherein at least one of the inverting means comprises an inverter circuit.

6. A frequency divider, comprising:

a first and a second triggered delay element, each having a data input, a trigger control input and a data output, the delay elements configured to forward a state of an input signal at their respective data input to their respective data output, wherein it depends on a control signal at the respective trigger control input of the delay element whether the state is forwarded either for a rising clock edge of an input clock signal or for a falling clock edge of the input clock signal; and

a clock output;

wherein the data input and the trigger control input of the first delay element are coupled to the clock output, wherein one input of said data input and said trigger control input is coupled to the clock output by first inverting means;

wherein the data input and the trigger control input of the second delay element are coupled to the data output of the first delay element, wherein one input of said data input and said trigger control input is coupled to said data output by second inverting means in a complementary fashion with respect to the first delay element; and

wherein the clock output is coupled to the data output of the second delay element.

7. A method for frequency division, comprising:

providing an input clock signal;

deriving a first input state of a plurality of at least two input states from a last data signal of a plurality of at least two data signals;

deriving a first selection signal of a plurality of at least two selection signals from the last data signal, the first selection signal pertaining to the first input state;

deriving a first data signal of the plurality of at least two data signals by forwarding the first input state, wherein it depends on the first selection signal whether the first input state is forwarded either at a rising clock edge of the input clock signal or at a falling clock edge of the input clock signal;

deriving a further input state of the plurality of at least two input states from a respective preceding data signal of the plurality of at least two data signals;

deriving a further selection signal of the plurality of at least two selection signals from the respective preceding data signal, the further selection signal pertaining to the further input state;

deriving a further data signal of the plurality of at least two data signals by forwarding the further input state, wherein it depends on the further selection signal whether the further input state is forwarded either at a rising clock edge of the input clock signal or at a falling clock edge of the input clock signal; and

deriving an output clock signal from one data signal of the plurality of at least two data signals;

wherein one of the plurality of at least two selection signals is derived by inverting the corresponding data signal and wherein the input states not pertaining to said one selection signal are derived by inverting the corresponding data signals.

8. The method according to claim 7, wherein deriving of a respective data signal of the plurality of at least two data signals comprises:

deriving a first auxiliary data signal by forwarding the respective state at a rising clock edge of the input clock signal;

deriving a second auxiliary data signal by forwarding the respective state at a falling clock edge of the input clock signal; and

selecting the first or the second auxiliary data signal as the respective data signal depending on the respective selection signal.

9. The method according to claim 7, wherein the signals processed are in a differential form.

10. The method according to claim 9, wherein inverted versions of differential signals are derived by swapping complementary components of the respective differential signal.