Apparatus and method for efficient level shift

• US 8,203,373 B2
• Filed: 08/04/2011
• Issued: 06/19/2012
• Est. Priority Date: 08/13/2009
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments Deutschland Gesellschaft Mit Beschrã¤Nkter Haftung (Texas Instruments, Inc.)
• Inventors: Herzer, Stefan, Stettner, Ferdinand, Wicht, Bernhard
• Primary Examiner(s): Le, Dinh T.
• Application Number:
  US13/198,339
• Publication Number:
  US 20110285449A1
• Time in Patent Office: 320 Days
• Field of Search: 326 62- 63, 326 80- 82, 327/306, 327/333
• US Class Current: 327/333
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

An apparatus is provided that uses a first level shifter for performing a voltage shift of a low level input signal of a first voltage domain to a high level output signal of a second voltage domain. The first level shifter comprises a storing element in the second voltage domain, an input stage coupled to the storing element for providing a signal state to be stored in the storing element and a feedback loop from an output of the storing element to the input stage for controlling the input stage in response to a transition of a high level output signal of the storing element.

Claims

1. An apparatus comprising:

an input circuit;

a first flip-flop that is coupled to the input stage, wherein the first flip-flop operates in a first voltage domain;

a reset circuit having a first capacitor that is coupled to the first flip-flop, wherein the reset circuit operates in a second voltage domain;

a set circuit having a second capacitor that is coupled to the first flip-flop, wherein the set circuit operates in the second voltage domain; and

a second flip-flop that is coupled to the set and reset circuits; and

a logic circuit that is coupled to the second flip-flop and the input circuit, and that receives an input signal.

2. The apparatus of claim 1, wherein the input circuit further comprises:

a first resistor that receives a first voltage from the first voltage domain and that is coupled to the first flip-flop;

a first MOS transistor that is coupled to the first resistor at its drain and that is coupled to the logic circuit at its gate;

a second resistor that receives the first voltage from the first voltage domain and that is coupled to the first flip-flop; and

a second MOS transistor that is coupled to the second resistor at its drain and that is coupled to the logic circuit at its gate.

3. The apparatus of claim 1, wherein the logic circuit further comprises:

an AND gate that is coupled to the first and second flip-flops and that receives the input signal; and

a NOR gate that is coupled to the first and second flip-flops and that receives the input signal.

4. The apparatus of claim 1, wherein the reset circuit further comprises an inverter that is coupled between the first capacitor and the second flip-flop.

5. The apparatus of claim 1, wherein the set circuit further comprises a plurality of inverters coupled in series with one another between the second capacitor and the second flip-flop.

6. An apparatus comprising:

a high voltage rail;

a low voltage rail;

a control circuit that is coupled to the low voltage rail;

a level shifter having;

an input circuit;

a first flip-flop that is coupled to the input stage and the high voltage rail;

a reset circuit having a first capacitor that is coupled to the first flip-flop and the low voltage rail;

a set circuit having a second capacitor that is coupled to the first flip-flop and the second voltage rail; and

a second flip-flop that is coupled to the set and reset circuits; and

a logic circuit that is coupled to the second flip-flop, the input circuit, and the control circuit;

a high side driver that is coupled to the first flip-flop;

a low side driver that is coupled to the control circuit;

a current sensing circuit that is adapted to receive a current feedback signal;

an error amplifier that is adapted to receive a voltage feedback signal; and

a summing comparator that is coupled to the current sensing circuit, the voltage sensing circuit, and the control circuit.

7. The apparatus of claim 6, wherein the input circuit further comprises:

a first resistor that receives a first voltage from the first voltage domain and that is coupled to the first flip-flop;

a first MOS transistor that is coupled to the first resistor at its drain and that is coupled to the logic circuit at its gate;

a second resistor that receives the first voltage from the first voltage domain and that is coupled to the first flip-flop; and

a second MOS transistor that is coupled to the second resistor at its drain and that is coupled to the logic circuit at its gate.

8. The apparatus of claim 6, wherein the logic circuit further comprises:

an AND gate that is coupled to the first flip-flop, the second flip-flops, and the control circuit; and

a NOR gate that is coupled to the first flip-flop, the second flip-flop, and the control circuit.

9. The apparatus of claim 6, wherein the reset circuit further comprises an inverter that is coupled between the first capacitor and the first input terminal of the second flip-flop.

10. The apparatus of claim 6, wherein the set circuit further comprises a plurality of inverters coupled in series with one another between the second capacitor and the second input terminal of the second flip-flop.

11. The apparatus of claim 6, wherein the apparatus further comprises:

a high side switch that is coupled to the high side driver and a switching node;

a low side switch that is coupled to the low side driver and the switching node;

an inductor that is coupled to the switching node;

a resistor-capacitor (RC) network that is coupled in parallel to the inductor, wherein the RC network is coupled to the current sensing circuit; and

a voltage divider that is coupled to the inductor and the error amplifier.