Memory controller for controlling write signaling
First Claim
1. A memory controller having an interface to convey:
- over a first set of interconnect resources;
a first command that specifies activation of a row of memory cells;
a second command that specifies a write operation directed to the row of memory cells;
a bit that specifies whether precharging will occur in connection with the write operation;
a code that specifies whether data mask information will be issued in connection with the write operation; and
if the code specifies that data mask information will be issued, data mask information that specifies whether to selectively write portions of write data associated with the write operation; and
over a second set of interconnect resources, separate from the first set of interconnect resource, the write data.
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Accused Products
Abstract
A memory controller has an interface to convey, over a first set of interconnect resources: a first command that specifies activation of a row of memory cells, a second command that specifies a write operation directed to the row of memory cells, a bit that specifies whether precharging will occur in connection with the write operation, a code that specifies whether data mask information will be issued in connection with the write operation, and if the code specifies that data mask information will be issued, data mask information that specifies whether to selectively write portions of write data associated with the write operation. The memory controller interface further conveys, over a second set of interconnect resources, separate from the first set of interconnect resource, the write data.
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Citations
21 Claims
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1. A memory controller having an interface to convey:
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over a first set of interconnect resources; a first command that specifies activation of a row of memory cells; a second command that specifies a write operation directed to the row of memory cells; a bit that specifies whether precharging will occur in connection with the write operation; a code that specifies whether data mask information will be issued in connection with the write operation; and if the code specifies that data mask information will be issued, data mask information that specifies whether to selectively write portions of write data associated with the write operation; and over a second set of interconnect resources, separate from the first set of interconnect resource, the write data. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A memory controller for controlling a memory device, comprising:
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a first interface portion to convey; a first command and a first bank address to activate a row in a bank identified by the first bank address; a second command and a second bank address, the second command specifying a write operation; a code that specifies whether data mask information will be issued in connection with the write operation; and if the data mask information will be issued in connection with the write operation, data mask information that specifies whether to selectively write portions of the write data, in connection with the write operation, to a bank identified by the second bank address; and a second interface portion to convey the write data. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A memory controller for controlling a memory device, comprising:
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an interface to convey; a first command that specifies activation of a row of memory cells; and a second command that specifies a write operation; and write data over a set of interconnect resources that are separate from interconnect resources used to convey the first command and the second command; wherein the interface conveys, to a first interconnect resource; a code that specifies whether data mask information will be issued in connection with the write operation, wherein the code is conveyed synchronously with respect to a first transition of a clock signal that is received by the memory device; and if the code specifies that the data mask information will be issued, two bits of the data mask information during a clock cycle of the clock signal, wherein if the data mask information is conveyed, the data mask information specifies whether to selectively write portions of the write data to the row of memory cells in connection with the write operation. - View Dependent Claims (19, 20, 21)
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Specification