Dynamically configured coprocessor for different extended instruction set personality specific to application program with shared memory storing instructions invisibly dispatched from host processor

• US 8,205,066 B2
• Filed: 10/31/2008
• Issued: 06/19/2012
• Est. Priority Date: 10/31/2008
• Status: Active Grant

• Current Assignee: Lenovo PC International Limited (Lenovo Group Ltd.), Micron Technology, Inc.
• Original Assignee: Convey Computer (Micron Technology, Inc.)
• Inventors: Wallach, Steven J., Brewer, Tony
• Primary Examiner(s): Kim, Kenneth
• Application Number:
  US12/263,203
• Publication Number:
  US 20100115237A1
• Time in Patent Office: 1,327 Days
• Field of Search: None
• US Class Current: 712/34
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3897 with adaptable data path

Abstract

A co-processor is provided that comprises one or more application engines that can be dynamically configured to a desired personality. For instance, the application engines may be dynamically configured to any of a plurality of different vector processing instruction sets, such as a single-precision vector processing instruction set and a double-precision vector processing instruction set. The co-processor further comprises a common infrastructure that is common across all of the different personalities, such as an instruction decode infrastructure, memory management infrastructure, system interface infrastructure, and/or scalar processing unit (that has a base set of instructions). Thus, the personality of the co-processor can be dynamically modified (by reconfiguring one or more application engines of the co-processor), while the common infrastructure of the co-processor remains consistent across the various personalities.

Claims

1. A method for processing data comprising:

initiating an executable file on a manufactured host processor of a system, said manufactured host processor having a predefined instruction set that is fixed such that it is not modifiable by a consumer, wherein the executable file contains native instructions that are natively supported by the host processor'"'"'s predefined instruction set and extended instructions that are not natively supported by the host processor'"'"'s predefined instruction set, wherein said extended instructions are present in the executable file as data to be stored to a memory by one or more of said native instructions;

configuring an application engine of a co-processor of the system, at system run-time, to fully possess a selected one of a plurality of different application-specific personalities, wherein the co-processor has an existing virtual memory and instruction decode infrastructure that is common across all of the plurality of different application-specific personalities, and wherein each of the plurality of different application-specific personalities comprises an extended instruction set having extended instructions that are not natively supported by the host processor'"'"'s instruction set, thereby extending the fixed instruction set of the host processor; and

processing the instructions of the executable file, wherein said native instructions of the executable file are processed by the host processor and said extended instructions of the executable file are processed by the co-processor, and wherein said host processor unknowingly dispatches said extended instructions of the executable file to the co-processor as a result of executing one or more native instructions of the executable file for writing the extended instructions to a designated portion of said memory that is accessible by said co-processor.

2. The method of claim 1 wherein said configuring comprises configuring at least one field-programmable gate array (FPGA) of said application engine.

3. The method of claim 1 further comprising:

receiving, by the co-processor, reconfiguration information pertaining to the selected personality.

4. The method of claim 3 wherein the receiving is performed dynamically during execution of an application for which the selected application-specific personality is desired.

5. The method of claim 1 wherein the application engine comprises function units that are configurable at system run-time to any of the plurality of different application-specific personalities, wherein the function units are compatible with the framework of the infrastructure, said infrastructure including virtual memory, physical memory, instruction structure and a register structure.

6. The method of claim 1 wherein said plurality of personalities comprise a plurality of vector processing personalities.

7. The method of claim 6 wherein said plurality of vector processing personalities comprise at least one of:

a single-precision vector processing personality and a double-precision vector processing personality.

8. The method of claim 1 further comprising:

identifying, from information contained in the executable file, the selected one of the plurality of different application-specific personalities for configuring the application engine of the co-processor.

9. The method of claim 1 wherein the host processor is implemented on a first integrated circuit, and wherein the co-processor is implemented external to said first integrated circuit.

10. The method of claim 1 wherein the plurality of different application-specific personalities are mutually-exclusive.

11. The method of claim 10 wherein the plurality of different application-specific personalities are stored to persistent data storage separate from the executable file, and wherein the configuring comprises loading the selected one of the plurality of different application-specific personalities from the persistent data storage to the application engine.

12. A system for processing data comprising:

at least one manufactured host processor having a predefined instruction set that is fixed such that it is not modifiable by a consumer;

a co-processor comprising;

at least one application engine having at least one configurable function unit that is configurable at system run-time to fully possess any of a plurality of different application-specific personalities, wherein each of the plurality of different application-specific personalities comprises an extended instruction set having extended instructions that are not natively supported by the host processor'"'"'s instruction set, thereby extending the instruction set of the host processor, and

a virtual memory and instruction decode infrastructure common to all the plurality of different application-specific personalities; and

wherein said manufactured host processor and said co-processor are operable to execute an executable file that contains both native instructions that are natively supported by the host processor'"'"'s instruction set and extended instructions that are not natively supported by the host processor'"'"'s instruction set, wherein said extended instructions are present in the executable file as data to be written to a memory by one or more of said native instructions, whereby said native instructions of the executable file are processed by the host processor and said host processor unknowingly dispatches extended instructions of the executable file to the co-processor for processing as a result of said host processor executing one or more native instructions of the executable file for writing the extended instructions to a designated portion of said memory that is accessible by said co-processor.

13. The system of claim 12 wherein the plurality of different application-specific personalities comprise a plurality of different vector processing personalities.

14. The system of claim 13 wherein said plurality of different vector processing personalities comprise at least one of:

a single-precision vector processing personality and a double-precision vector processing personality.

15. A co-processor comprising:

a system interface infrastructure for interfacing with a manufactured host processor that has a predefined instruction set that is fixed such that the predefined instruction set is not modifiable by a consumer,

at least one application engine having at least one configurable function unit that is configurable at system run-time to fully possess any of a plurality of different, mutually-exclusive application-specific vector processing personalities, wherein each of the plurality of application-specific vector processing personalities comprises an extended instruction set having extended instructions that are not natively supported by the host processor'"'"'s instruction set, thereby extending the fixed instruction set of the host processor;

a co-processor infrastructure common to all the plurality of different application-specific vector processing personalities; and

wherein said co-processor is operable with said manufactured host processor to execute an executable file that contains both native instructions that are natively supported by the host processor'"'"'s instruction set and extended instructions that are not natively supported by the host processor'"'"'s instruction set, wherein said extended instructions are present in the executable file as data to be written to a memory by one or more of said native instructions, whereby said native instructions of the executable file are processed by the host processor and said extended instructions of the executable file are processed by the co-processor.

16. The co-processor of claim 15 wherein the co-processor infrastructure comprises:

a memory management infrastructure, where said memory management infrastructure is common to all the plurality of different application-specific vector processing personalities.

17. The co-processor of claim 15 wherein said system interface infrastructure is common to all the plurality of different application-specific vector processing personalities.

18. The co-processor of claim 15 wherein the co-processor infrastructure comprises:

an instruction decode infrastructure, where said instruction decode infrastructure is common to all the plurality of different application-specific vector processing personalities.

19. The co-processor of claim 15 wherein the co-processor infrastructure comprises:

a scalar processing unit that comprises a fixed set of instructions, where said scalar processing unit is common to all the plurality of different application-specific vector processing personalities.

20. The co-processor of claim 15 wherein the co-processor infrastructure comprises:

a memory management infrastructure, said system interface infrastructure for interfacing with said host processor, and an instruction decode infrastructure that are common to all the plurality of different application-specific vector processing personalities.

21. The co-processor of claim 20 wherein the co-processor infrastructure further comprises:

a scalar processing unit that comprises a fixed set of instructions, where said scalar processing unit is common to all the plurality of different application-specific vector processing personalities.

22. The co-processor of claim 15 wherein said plurality of different application-specific vector processing personalities comprise at least one of:

a single-precision vector processing personality and a double-precision vector processing personality.

23. The co-processor of claim 15 wherein the manufactured host processor is implemented on a first integrated circuit, and the co-processor is implemented external to the first integrated circuit.

24. The co-processor of claim 15 wherein a selected one of the plurality of different application-specific vector processing personalities is identified, from information contained in the executable file, for configuring the at least one configurable function unit of the co-processor.

25. A system comprising:

a host processor having a predefined fixed instruction set; and

a co-processor, said co-processor including

at least one configurable function unit that is configurable at system run-time to fully possess any of a plurality of different, mutually-exclusive vector processing personalities, wherein each of the plurality of different vector processing personalities comprises an extended instruction set having extended instructions that are not natively supported by the host processor'"'"'s instruction set, thereby extending the predefined fixed instruction set of the host processor, and

a virtual memory and instruction decode infrastructure that is common to all the plurality of different vector processing personalities;

wherein an executable file executing on said host processor contains both native instructions that are natively supported by the host processor'"'"'s instruction set and extended instructions that are not natively supported by the host processor'"'"'s instruction set, and wherein said extended instructions are present in the executable file as data to be written by one or more of said native instructions to a memory that is accessible by said co-processor.

26. The system of claim 25 wherein said plurality of different vector processing personalities comprise at least one of:

a single-precision vector processing personality and a double-precision vector processing personality.

27. The system of claim 25 wherein said co-processor is operable with said manufactured host processor to execute said executable file.

28. The system of claim 27 wherein writing the extended instructions by the one or more native instructions to said memory causes the host processor to unknowingly dispatch said extended instructions to said co-processor.

29. The system of claim 28 wherein said native instructions cause the host processor to load said extended instructions to a pre-designated portion of said memory that is accessible by said co-processor.

30. A system comprising:

a manufactured host processor having a predefined fixed instruction set that is not modifiable by a consumer;

a dynamically reconfigurable co-processor comprising reconfigurable function units that can be dynamically configured, at system run-time, to fully possess any selected one of a plurality of different, mutually-exclusive vector processing personalities for performing corresponding operations of the selected vector processing personality, wherein each of the plurality of different vector processing personalities comprises an extended instruction set having extended instructions that are not natively supported by the host processor'"'"'s instruction set, thereby extending the fixed instruction set of the host processor;

said dynamically reconfigurable co-processor further comprising an infrastructure that is common to all the plurality of different vector processing personalities;

wherein said dynamically reconfigurable co-processor is operable with said manufactured host processor to execute an executable file that contains both native instructions that are natively supported by the host processor'"'"'s instruction set and extended instructions that are not natively supported by the host processor'"'"'s instruction set, wherein said extended instructions are present in the executable file as data to be loaded to a memory by one or more of said native instructions; and

wherein the executable file contains native instructions that when executed by the host processor causes the host processor to unknowingly dispatch said extended instructions to said co-processor by loading the extended instructions to a pre-designated portion of said memory that is accessible by said co-processor.

31. The system of claim 30 wherein the infrastructure comprises:

a memory management infrastructure, a system interface infrastructure for interfacing with said host processor, and an instruction decode infrastructure that are common to all the plurality of different vector processing personalities.

32. The system of claim 31 wherein the infrastructure further comprises:

a scalar processing unit that comprises a fixed set of instructions, where said scalar processing unit is common to all the plurality of different vector processing personalities.

33. The system of claim 30 wherein said plurality of different vector processing personalities comprise at least:

a single-precision vector processing personality and a double-precision vector processing personality.

34. A method comprising:

initiating an executable file on a manufactured host processor that has a predefined instruction set that is fixed such that it is not modifiable by a consumer, wherein the executable file contains native instructions that are natively supported by the host processor'"'"'s predefined instruction set and extended instructions that are not natively supported by the host processor'"'"'s predefined instruction set, wherein said extended instructions are present in the executable file as data to be written by one or more of said native instructions to a designated portion of a memory that is accessible by a reconfigurable co-processor;

configuring said reconfigurable co-processor to fully possess a selected one of a plurality of different, mutually-exclusive vector processing personalities for processing a portion of the instructions of the executable file, wherein each of the plurality of different predefined vector processing personalities comprises an extended instruction set having extended instructions that are not natively supported by the host processor'"'"'s instruction set, thereby extending the fixed instruction set of the host processor;

processing the instructions of the executable file, wherein said native instructions of the executable file are processed by the host processor and said extended instructions of the executable file are processed by the reconfigurable co-processor.

35. The method of claim 34 wherein said plurality of different vector processing personalities comprise at least:

a single-precision vector processing personality and a double-precision vector processing personality.

36. The method of claim 34 wherein the manufactured host processor is implemented on a first integrated circuit, and wherein the co-processor is implemented external to said first integrated circuit.

37. A method comprising:

initiating an executable file on a manufactured host processor that has a predefined instruction set that is fixed such that it is not modifiable by a consumer, wherein the executable file contains native instructions that are natively supported by the host processor'"'"'s predefined instruction set and extended instructions that are not natively supported by the host processor'"'"'s predefined instruction set, wherein said extended instructions are present in the executable file as data to be written by one or more of said native instructions to a memory;

determining one of a plurality of different, mutually-exclusive vector processing personalities to load to a dynamically reconfigurable co-processor for processing a portion of the instructions of the executable file, wherein the determined vector processing personality defines an extended instruction set that comprises instructions for performing vector oriented operations that are not natively supported by the host processor'"'"'s predefined instruction set, thereby extending the host processor'"'"'s instruction set;

when determined that the determined vector processing personality is not present on the dynamically reconfigurable co-processor, fully loading, at system run-time, the determined vector processing personality to the dynamically reconfigurable co-processor; and

processing the instructions of the executable file, wherein the native instructions of the executable file are processed by the host processor and the extended instructions of the executable file are processed by the dynamically reconfigurable co-processor, wherein said host processor unknowingly dispatches said extended instructions of the executable file to the co-processor as a result of executing one or more native instructions of the executable file for writing the extended instructions to a designated portion of said memory that is accessible by said co-processor.

38. The method of claim 37 wherein said plurality of different vector processing personalities comprise at least:

a single-precision vector processing personality and a double-precision vector processing personality.

39. The method of claim 37 wherein the manufactured host processor is implemented on a first integrated circuit, and wherein the co-processor is implemented external to said first integrated circuit.

40. A system comprising:

a manufactured host processor implemented on a first integrated circuit and comprising a predefined fixed instruction set that is not modifiable by a consumer; and

a co-processor implemented external to said first integrated circuit and comprising reconfigurable logic for dynamically reconfiguring the co-processor to possess any of a plurality of different vector processing personalities, wherein each of said plurality of different vector processing personalities comprises an extended instruction set providing extended instructions not natively supported by the host processor'"'"'s instruction set, thereby extending the host processor'"'"'s instruction set; and

wherein said manufactured host processor and said co-processor are operable to execute an executable file that contains both native instructions that are natively supported by the host processor'"'"'s instruction set and extended instructions that are not natively supported by the host processor'"'"'s instruction set, wherein said extended instructions are present in the executable file as data to be written by one or more of said native instructions to a memory, whereby said host processor unknowingly dispatches said extended instructions of the executable file to the co-processor as a result of executing one or more native instructions of the executable file for writing the extended instructions to a designated portion of said memory that is accessible by said co-processor.

41. The system of claim 40 wherein said host processor and said co-processor share a common virtual address space.

42. The system of claim 41 further comprising:

each of said host processor and said co-processor comprising a respective local cache, wherein cache coherency is maintained between the host processor and co-processor.

43. The system of claim 40 further comprising:

said executable file, wherein said native instructions are for processing by said host processor and said extended instructions are for processing by said co-processor.

44. The system of claim 43 wherein all memory addresses for all of said native and extended instructions in the executable are virtual addresses.