Automatic synthesis of clock distribution networks

• US 8,205,182 B1
• Filed: 08/22/2008
• Issued: 06/19/2012
• Est. Priority Date: 08/22/2007
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Zlatanovici, Radu, Albrecht, Christoph, Tiwary, Saurabh Kumar
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US12/197,123
• Time in Patent Office: 1,397 Days
• Field of Search: 703/16, 716/105, 716/125, 716/6, 716/7, 716/9, 716/10, 716/13, 716/14, 716/113, 716/114, 716/122, 716/124, 716/126, 716/134
• US Class Current: 716/125
• CPC Class Codes: G06F 2117/04 Clock gating
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/396 Clock trees
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

In one embodiment of the invention, a method for designing an integrated circuit is disclosed. The method includes automatically partitioning clock sinks of an integrated circuit design into a plurality of partitions; automatically synthesizing a clock tree from a master clock generator into the plurality of partitions to minimize local clock skew within each of the plurality of partitions; and automatically synthesizing clock de-skew circuitry into each of the plurality of partitions to control clock skew between neighboring partitions.

Claims

1. A method for designing an integrated circuit, the method comprising using a processor to perform one or more of the following:

automatically partitioning clock sinks of an integrated circuit design into a plurality of partitions for each clock source;

automatically synthesizing an intra-partition clock network from a local root within each of the plurality of partitions to minimize local clock skew within each of the plurality of partitions; and

automatically synthesizing clock de-skew circuitry into each of the plurality of partitions to control clock skew between neighboring partitions for each clock source.

2. The method of claim 1, wherein

placement of the clock sinks is a timing driven placement responsive to timing slack in critical data paths having source and destination points in different partitions.

3. The method of claim 1, wherein

the partitioning of clock sinks is in response to signal connectivity and signal timing along critical data paths.

4. The method of claim 1, wherein

the automatic partitioning of clock sinks is in response to a physical placement of the clock sinks.

5. The method of claim 1, wherein

the local skew within each of the plurality of partitions is minimized to be less than or equal to a value of a maximum local clock skew design parameter.

6. The method of claim 1, wherein

a clock sink is a latch with a clock input terminal.

7. The method of claim 1, wherein

a clock sink is a flip flop with a clock input terminal.

8. The method of claim 1, wherein

the clock de-skew circuitry is coupled between a master clock generator and the clock sinks in each partition.

9. The method of claim 1, wherein

the clock de-skew circuitry is synthesized into each of the plurality of partitions with a clock control step size that is responsive to a sum of the local clock skew (l) and the clock control step size (s) being less than a guard band level (g).

10. The method of claim 1, wherein

the clock de-skew circuitry is synthesized into each of the plurality of partitions with a clock control step size (s) less than a sum of the maximum local clock skew (l) and a guard band level (g).

11. The method of claim 1, wherein

the clock de-skew circuitry includes

one or more phase detectors coupled between one or more neighboring partitions, and

a de-skew control circuit within each partition coupled to the one or more phase detectors.

12. The method of claim 1, wherein

the automatic partitioning of clock sinks includes

positioning partitions near each other to minimize a number of partitions over which a critical signal path crosses.

13. The method of claim 1, wherein

the automatic partitioning of clock sinks is performed hierarchically.

14. The method of claim 13, wherein

one level of the hierarchy of the clock partitions includes boundaries of the various voltage islands.

15. The method of claim 1, wherein

the clock de-skew circuitry includes a level shifter to receive a first clock signal having first voltage levels different from second voltage levels of a second clock signal, the level shifter to shift the first voltage levels towards second voltage levels to compare the first clock signal and the second clock signal.

16. The method of claim 1, further comprising:

automatically synthesizing a global clock network from a master clock generator for each clock source that is coupled to the clock de-skew circuitry within each of the plurality of partitions.

17. The method of claim 1, wherein

the automatically synthesizing of the intra-partition clock network includes

automatically synthesizing a tree network of wires within a partition;

and

automatically synthesizing a mesh network of wires within the partition.

18. The method of claim 1, wherein

the automatically synthesizing of the intra-partition clock network is in response to timing, placement, and connectivity of circuits.

19. A machine-readable product comprising:

a non-transitory machine readable medium having machine readable program code stored therein that is executable by a machine to design an integrated circuit including

machine readable program code to automatically partition clock sinks of an integrated circuit design into a plurality of partitions;

machine readable program code to automatically synthesize an intra-partition clock network from a local root within each of the plurality of partitions to minimize local clock skew within each of the plurality of partitions; and

machine readable program code to automatically synthesize clock de-skew circuitry into each of the plurality of partitions to control clock skew between neighboring partitions for each clock source.

20. The machine-readable product of claim 19, wherein the non-transitory machine readable medium further has stored therein

machine readable program code to automatically synthesize a global clock network from a master clock generator for each clock source that is coupled to the clock de-skew circuitry within each of the plurality of partitions.

21. The machine-readable product of claim 19, wherein

the clock de-skew circuitry includes

one or more phase detectors coupled between one or more neighboring partitions, and

a de-skew control circuit within each partition coupled to the one or more phase detectors.

22. The machine-readable product of claim 21, wherein

the clock de-skew circuitry further includes

a level shifter to receive a first clock signal having first voltage levels different from second voltage levels of a second clock signal, the level shifter to shift the first voltage levels towards second voltage levels to compare the first clock signal and the second clock signal.

23. A system to design an integrated circuit, the system comprising:

a processor;

a processor readable medium coupled to the processor, the processor readable medium to store instructions that when executed by the processor cause the processor to perform operations to automatically synthesize a clock distribution network for an integrated circuit design, the operations including

partitioning clock sinks of an integrated circuit design into a plurality of partitions;

synthesizing an intra-partition clock network from a local root within each of the plurality of partitions to minimize local clock skew within each of the plurality of partitions; and

synthesizing clock de-skew circuitry into each of the plurality of partitions to control clock skew between neighboring partitions for each clock source.

24. The system of claim 23, wherein the processor executes further instructions to perform operations of

synthesizing a global clock network from a master clock generator for each clock source that is coupled to the clock de-skew circuitry within each of the plurality of partitions.

25. The system of claim 23 wherein

the partitioning of clock sinks includes

positioning partitions near each other to minimize a number of partitions over which a critical signal path crosses.