Process for maintaining execution synchronization between several asynchronous processors working in parallel and in a redundant manner

• US 8,205,201 B2
• Filed: 02/13/2008
• Issued: 06/19/2012
• Est. Priority Date: 02/13/2007
• Status: Expired due to Fees

• Current Assignee: Thales SA
• Original Assignee: Thales SA
• Inventors: Ple, Christophe
• Primary Examiner(s): To, Jennifer
• Application Number:
  US12/030,461
• Publication Number:
  US 20080196037A1
• Time in Patent Office: 1,588 Days
• Field of Search: 718/107, 718/102
• US Class Current: 718/102
• CPC Class Codes: G06F 11/1683 at instruction level
• CPC Class Codes: G06F 11/1687 at event level, e.g. by interrupt or result of polling
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A process for maintaining synchronization of processors that are executing a same plurality of applications in parallel includes interrupting a current task between processing two successive instructions of an application being processed when an interrupt request occurs to process another application. An intermediate state reached by the current task is saved when the interrupt request occurs, and a counter for each of the processors indicating a number of instructions processed by each of the processors is maintained. A processor is caused to issue a synchronization confirmation in response to a comparison result that the numbers of instructions processed are identical. The processor is caused to enter a wait state when its number of processed-instructions is the largest among the processors or to execute a procedure for processing the instructions until its processed-instruction counter reaches the largest number.

Claims

1. A process for maintaining synchronization, in a computer with parallel processing units, between processors of the processing units in which all the processors are executing a same plurality of applications in parallel and at the same speed but in an asynchronous manner under a control of a common multi-tasking operating system, the process comprising:

interrupting, by each of the processors, a current task between processing two successive instructions of an application being processed when an interrupt request occurs to process another application;

saving an intermediate state reached by the current task when the interrupt request occurs;

maintaining a counter for each of the processors indicating a number of instructions processed by each of the processors apart from process instructions;

managing the resources of the computer by system calls generated by the plurality of applications, wherein the system calls trigger software interrupts;

sharing time in successive time slices of which each is allocated to processing an application from the plurality of applications, wherein sharing is performed by timing interrupt requests issued by the common multi-tasking operating system to each processor at the end of a time slice in order to cause a change process from a current application to another application to be executed, the change process comprising saving of the intermediate state that was reached by the current application when interrupted and restoration of a last intermediate state that was saved for another application to be executed with resynchronization of the processed-instruction counters of the processors;

maintaining synchronization using a synchronization procedure called by a synchronization interrupt request issued by the common multi-tasking operating system to all the processors;

signaling by a processor to other processors a number of processed instructions contained in its processed-instruction counter;

comparing the number of processed instructions contained in its processed-instruction counter with the numbers of processed instructions contained in the processed-instruction counters of the other processors after they accepted the synchronization interrupt;

causing the processor to issue a synchronization confirmation in response to a comparison result that the numbers of instructions processed are identical; and

causing the processor to enter a wait state when its number of processed-instructions is the largest of the numbers of instructions processed that are compared and the comparison is repeated for each new exchange of numbers of instructions processed with the other processors, or causing the processor to execute a procedure for processing the instructions step-by-step until its processed-instruction counter reaches the largest number and then the processor sends to the other processors an updated value of its number of instructions processed, with renewal of the comparison;

wherein the synchronization procedure is activated at the beginning of the processing of each timing interrupt generated by the common multi-tasking operating system at the end of a time slice and of each system call generated by an application.

2. The process according to claim 1, further comprising causing a reset of all the processors after one of the processors being in the wait state exceeding a certain duration.

3. The process according to claim 1, further comprising causing a reset of all the processors if one of the processors is executing the synchronization procedure following a system call generated by an application or following detection of a hardware or software error, and another one of the processors is processing a timing interrupt request with a processed-instruction counter indicating a number greater than that of a processed-instruction counter of the another one of the processors.

4. The process according to claim 1, further comprising causing a reset of all the processors if one of the processors is executing the synchronization procedure and another one of the processors is processing an interrupt request in connection with a hardware or software error and if, on completion of the synchronization procedure, the processors do not all converge on an identical error situation.