Manufacturing method of semiconductor device

• US 8,207,025 B2
• Filed: 04/01/2011
• Issued: 06/26/2012
• Est. Priority Date: 04/09/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Suzawa, Hideomi, Sasagawa, Shinya
• Primary Examiner(s): GHYKA, ALEXANDER G
• Application Number:
  US13/078,020
• Publication Number:
  US 20110250723A1
• Time in Patent Office: 452 Days
• Field of Search: 438/151, 438/161
• US Class Current: 438/151
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78636 with supplementary region or layer for improving the flatness of the device
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

In an embodiment, an insulating film is formed over a flat surface; a mask is formed over the insulating film; a slimming process is performed on the mask; an etching process is performed on the insulating film using the mask; a conductive film covering the insulating film is formed; a polishing process is performed on the conductive film and the insulating film, so that the conductive film and the insulating film have equal thicknesses; the conductive film is etched, so that a source electrode and a drain electrode which are thinner than the conductive film are formed; an oxide semiconductor film is formed in contact with the insulating film, the source electrode, and the drain electrode; a gate insulating film covering the oxide semiconductor film is formed; and a gate electrode is formed in a region which is over the gate insulating film and overlaps with the insulating film.

Claims

1. A manufacturing method of a semiconductor device comprising the steps of:

forming a first insulating film over a surface;

forming a first mask over the first insulating film;

performing a slimming process on the first mask, so that a second mask is formed;

performing an etching process on the first insulating film using the second mask, so that a second insulating film is formed;

forming a first conductive film over the second insulating film;

performing a polishing process on the first conductive film and the second insulating film, so that a second conductive film and a third insulating film having equal thicknesses are formed;

etching the second conductive film, so that a source electrode and a drain electrode which are thinner than the second conductive film are formed;

forming an oxide semiconductor film in contact with the third insulating film, the source electrode, and the drain electrode;

forming a gate insulating film over the oxide semiconductor film; and

forming a gate electrode in a region which is over the gate insulating film and overlaps with the third insulating film.

2. The manufacturing method of a semiconductor device according to claim 1, wherein the source electrode and the drain electrode are formed thinner than the third insulating film by 5 nm or more and 20 nm or less.

3. The manufacturing method of a semiconductor device according to claim 1, wherein the third insulating film has a thickness substantially equal to a thickness of the second insulating film.

4. The manufacturing method of a semiconductor device according to claim 1, wherein the surface is a flat surface having a root-mean-square roughness of less than or equal to 1 nm.

5. The manufacturing method of a semiconductor device according to claim 1, wherein the slimming process is performed using an ashing process using an oxygen radical.

6. The manufacturing method of a semiconductor device according to claim 1, wherein the polishing process is performed using chemical mechanical polishing.

7. The manufacturing method of a semiconductor device according to claim 1, wherein the first insulating film is formed by sputtering.

8. A manufacturing method of a semiconductor device comprising the steps of:

forming a first insulating film over a surface;

forming a first mask over the first insulating film;

performing a slimming process on the first mask, so that a second mask is formed;

performing an etching process on the first insulating film using the second mask, so that a second insulating film is formed;

forming a first conductive film over the second insulating film;

performing a polishing process on the first conductive film and the second insulating film, so that a second conductive film and a third insulating film having equal thicknesses are formed;

etching the second conductive film and the third insulating film, so that a fourth insulating film whose corner is removed and a source electrode and a drain electrode which are thinner than the second conductive film and the fourth insulating film are formed;

forming an oxide semiconductor film in contact with the fourth insulating film, the source electrode, and the drain electrode;

forming a gate insulating film over the oxide semiconductor film; and

forming a gate electrode in a region which is over the gate insulating film and overlaps with the fourth insulating film.

9. The manufacturing method of a semiconductor device according to claim 8, wherein the source electrode and the drain electrode are formed thinner than the fourth insulating film by 5 nm or more and 20 nm or less.

10. The manufacturing method of a semiconductor device according to claim 8, wherein the third insulating film has a thickness substantially equal to a thickness of the second insulating film.

11. The manufacturing method of a semiconductor device according to claim 8, wherein the surface is a flat surface having a root-mean-square roughness of less than or equal to 1 nm.

12. The manufacturing method of a semiconductor device according to claim 8, wherein the slimming process is performed using an ashing process using an oxygen radical.

13. The manufacturing method of a semiconductor device according to claim 8, wherein the polishing process is performed using chemical mechanical polishing.

14. The manufacturing method of a semiconductor device according to claim 8, wherein the first insulating film is formed by sputtering.

15. A manufacturing method of a semiconductor device comprising the steps of:

forming a first transistor including a channel formation region, a first gate insulating film over the channel formation region, a first gate electrode which is over the first gate insulating film and overlaps with the channel formation region, and a first source electrode and a first drain electrode which are electrically connected to the channel formation region;

forming an interlayer insulating film over the first transistor;

forming a first insulating film over the interlayer insulating film;

forming a first mask over the first insulating film;

performing a slimming process on the first mask, so that a second mask is formed;

performing an etching process on the first insulating film using the second mask, so that a second insulating film is formed;

forming a first conductive film over the second insulating film;

performing a polishing process on the first conductive film and the second insulating film, so that a second conductive film and a third insulating film having equal thicknesses are formed;

etching the second conductive film to form a second source electrode and a second drain electrode which are thinner than the second conductive film;

forming an oxide semiconductor film in contact with the third insulating film, the second source electrode, and the second drain electrode;

forming a second gate insulating film over the oxide semiconductor film; and

forming a second gate electrode in a region which is over the second gate insulating film and overlaps with the third insulating film.

16. The manufacturing method of a semiconductor device according to claim 15, wherein the second source electrode and the second drain electrode are formed thinner than the third insulating film by 5 nm or more and 20 nm or less.

17. The manufacturing method of a semiconductor device according to claim 15, wherein the third insulating film has a thickness substantially equal to a thickness of the second insulating film.

18. The manufacturing method of a semiconductor device according to claim 15, wherein the interlayer insulating film has a flat surface having a root-mean-square roughness of less than or equal to 1 nm

19. The manufacturing method of a semiconductor device according to claim 15, wherein the slimming process is performed using an ashing process using an oxygen radical.

20. The manufacturing method of a semiconductor device according to claim 15, wherein the polishing process is performed using chemical mechanical polishing.

21. The manufacturing method of a semiconductor device according to claim 15, wherein the first insulating film is formed by sputtering.

22. A manufacturing method of a semiconductor device comprising the steps of:

forming a first transistor including a channel formation region, a first gate insulating film over the channel formation region, a first gate electrode which is over the first gate insulating film and overlaps with the channel formation region, and a first source electrode and a first drain electrode which are electrically connected to the channel formation region;

forming an interlayer insulating film over the first transistor;

forming a first insulating film over the interlayer insulating film;

forming a first mask over the first insulating film;

performing a slimming process on the first mask, so that a second mask is formed;

performing an etching process on the first insulating film using the second mask, so that a second insulating film is formed;

forming a first conductive film over the second insulating film;

performing a polishing process on the first conductive film and the second insulating film, so that a second conductive film and a third insulating film having equal thicknesses are formed;

etching the second conductive film and the third insulating film to form a fourth insulating film whose corner is removed and a second source electrode and a second drain electrode which are thinner than the second conductive film and the fourth insulating film;

forming an oxide semiconductor film in contact with the fourth insulating film, the second source electrode, and the second drain electrode;

forming a second gate insulating film over the oxide semiconductor film; and

forming a second gate electrode in a region which is over the second gate insulating film and overlaps with the fourth insulating film.

23. The manufacturing method of a semiconductor device according to claim 22, wherein the second source electrode and the second drain electrode are formed thinner than the fourth insulating film by 5 nm or more and 20 nm or less.

24. The manufacturing method of a semiconductor device according to claim 22, wherein the third insulating film has a thickness substantially equal to a thickness of the second insulating film.

25. The manufacturing method of a semiconductor device according to claim 22, wherein the interlayer insulating film has a flat surface having a root-mean-square roughness of less than or equal to 1 nm.

26. The manufacturing method of a semiconductor device according to claim 22, wherein the slimming process is performed using an ashing process using an oxygen radical.

27. The manufacturing method of a semiconductor device according to claim 22, wherein the polishing process is performed using chemical mechanical polishing.

28. The manufacturing method of a semiconductor device according to claim 22, wherein the first insulating film is formed by sputtering.