Method for manufacturing a semiconductor component that includes a field plate

• US 8,207,037 B2
• Filed: 10/31/2007
• Issued: 06/26/2012
• Est. Priority Date: 10/31/2007
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Wang, Hui, Nemtsev, Gennadiy, Zheng, Yingping, Grivna, Gordon M.
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US11/931,606
• Publication Number:
  US 20090108342A1
• Time in Patent Office: 1,700 Days
• Field of Search: 438268-274, 438/E27.096, 438/E27.055, 438/E27.058
• US Class Current: 438/268
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A semiconductor component that includes a field plate and a semiconductor device and a method of manufacturing the semiconductor component. A semiconductor material includes an epitaxial layer disposed on a semiconductor substrate. A trench having an upper portion and a lower portion is formed in the epitaxial layer. A portion of a field plate is formed in the lower portion of the trench, wherein the field plate is electrically isolated from trench sidewalls. A gate structure is formed in the upper portion of the trench, wherein a gate oxide is formed from opposing sidewalls of the trench. Gate electrodes are formed adjacent to the gate oxide formed from the opposing sidewalls and a dielectric material is formed adjacent to the gate electrode. Another portion of the field plate is formed in the upper portion of the trench and cooperates with the portion of the field plate formed in the lower portion of the trench to form the field plate.

Claims

1. A method for manufacturing a semiconductor component, comprising:

providing a first semiconductor material having first and second opposing surfaces;

forming at least one trench in the first semiconductor material, the at least one trench having at least one sidewall and first and second trench regions, the second trench region between the first surface and the first trench region;

forming a dielectric material in the at least one trench, the dielectric material extending from the second trench region to the first trench region;

forming a second semiconductor material in the first trench region of the at least one trench, the dielectric material between the second semiconductor material and the at least one sidewall of the at least one trench, the second semiconductor material serving as a first portion of a field plate;

removing a portion of the dielectric material from the second trench region of the at least one trench to expose a portion of the at least one sidewall;

forming a gate structure within the second trench region of the at least one trench and adjacent to the exposed portion of the at least one sidewall; and

forming a third semiconductor material within the second trench region of the at least one trench, the third semiconductor material electrically separated from the gate structure and electrically coupled to the second semiconductor material, the third semiconductor material serving as a second portion of the field plate.

2. The method of claim 1, wherein the at least one sidewall comprises first and second sidewalls, and wherein forming the dielectric material in the at least one trench includes forming a first portion of the dielectric material adjacent the first sidewall and forming a second portion of the dielectric material adjacent the second sidewall, and forming the second semiconductor material in the at least one trench includes forming the second semiconductor material between first and second portions of the dielectric material.

3. The method of claim 2, further including:

removing a portion of the second semiconductor material between the first and second portions of the dielectric material to form a first electrically conductive structure; and

wherein removing a portion of the dielectric material from the second portion of the at least one trench to expose a portion of the at least one sidewall includes removing subportions of the first and second portions of the dielectric material.

4. The method of claim 3, further including:

forming dielectric material from portions of the first and second sidewalls of the at least one trench; and

forming a gate electrode adjacent the dielectric material formed from the first and second sidewalls of the at least one trench.

5. The method of claim 4, wherein forming the dielectric material includes oxidizing portions of the first semiconductor material exposed by the at least one trench and wherein forming the gate electrode includes depositing an electrically conductive material adjacent the dielectric material formed from the portions of the first and second sidewalls of the at least one trench.

6. The method of claim 1, further including forming a source region in a portion of the semiconductor material laterally adjacent the at least one trench.

7. The method of claim 1, wherein forming the gate structure within the second trench region of the at least one trench and adjacent to the exposed portion of the at least one sidewall includes:

forming dielectric material from or on the exposed portion of the at least one sidewall; and

forming a gate electrode adjacent the dielectric material formed from the exposed portion of the at least one sidewall.

8. The method of claim 1, wherein forming the second semiconductor material in the first trench region of the at least one trench includes forming a first polysilicon layer in the first trench region and forming the third semiconductor material in the second trench region of the at least one trench includes forming a second polysilicon layer in the second trench region.

9. A method for manufacturing a semiconductor component, comprising:

providing a first semiconductor material having first and second opposing surfaces;

forming at least one trench in the first semiconductor material, the at least one trench having first and second sidewalls;

forming a dielectric material in the at least one trench, a first portion of the dielectric material adjacent the first sidewall and a second portion of the dielectric material adjacent the second sidewall;

forming a second semiconductor material in the at least one trench, the dielectric material between the second semiconductor material and the at least one sidewall of the at least one trench and between first and second portions of the dielectric material;

removing a portion of the second semiconductor material between the first and second portions of the dielectric material to form a first electrically conductive structure;

forming a first portion of a gate structure within the at least one trench by;

removing subportions of the dielectric material;

forming dielectric material from portions of the first and second sidewalls of the at least one trench by oxidizing portions of the first semiconductor material exposed by the at least one trench; and

forming a gate electrode adjacent the dielectric material formed from the first and second sidewalls of the at least one trench by depositing an electrically conductive material adjacent the dielectric material formed from the portions of the first and second sidewalls of the at least one trench;

forming a third semiconductor material within the at least one trench, the third semiconductor material electrically separated from the gate structure; and

forming a layer of dielectric material over the electrically conductive material and removing portions of the layer of dielectric material to form first and second dielectric barriers that are laterally spaced apart from the first and second sidewalls of the at least one trench, wherein the first and second dielectric barriers have first and second sides;

removing a portion of the electrically conductive material between the first side of the first dielectric barrier and the first sidewall; and

removing a portion of the electrically conductive material between the first side of the second dielectric barrier and the second sidewall.

10. The method of claim 9, wherein the electrically conductive material comprises one of a doped layer of polysilicon or multi-layer structure comprising a silicide between first and second doped layers of polysilicon.

11. The method of claim 9, further including:

forming a first dielectric material between the first dielectric barrier and the first sidewall;

forming a second dielectric material between the second dielectric barrier and the second sidewall;

forming a third dielectric material laterally adjacent the second side of the first dielectric barrier; and

forming a fourth dielectric material laterally adjacent the second side of the second dielectric barrier.

12. The method of claim 11, further including forming an electrically conductive plug between the second sides of the first and second dielectric barriers and over the electrically conductive structure.

13. The method of claim 12, further including forming a doped region in a portion of the first semiconductor material adjacent the first surface.

14. The method of claim 12, further including forming a contact structure to the electrically conductive plug.

15. A method for manufacturing a semiconductor component, comprising:

providing a semiconductor substrate of a first conductivity type;

forming an epitaxial layer of the first conductivity type and a first resistivity over the semiconductor substrate, the epitaxial layer having a major surface;

forming a trench in the epitaxial layer, the trench having first and second sidewalls and a second trench region over a first trench region, wherein the first and second sidewalls extend into the first and second trench regions;

forming a first layer of dielectric material in the first and second trench regions;

forming a first portion of a field plate in the first trench region;

removing portions of the first layer of dielectric material to expose portions of the first and second sidewalls in the second trench region and portions of the epitaxial layer adjacent to the second trench region, wherein the portions of the first layer of dielectric material on the first and second sidewalls in the first trench region remain;

forming a gate dielectric adjacent the exposed portion of the first sidewall of the second trench region and from a the exposed portion of the epitaxial layer;

forming a gate electrode in the second trench region, the gate electrode adjacent the gate dielectric;

forming a dielectric material adjacent the gate electrode; and

forming a conductive plug in the second trench region, the conductive plug serving as a second portion of the field plate, electrically coupled to the first portion of the field plate, and electrically isolated from the gate electrode.

16. The method of claim 15, wherein forming the first portion of the field plate in the first region includes forming a dielectric material adjacent the first and second sidewalls and forming the first portion of the field plate adjacent the dielectric material, wherein the dielectric material electrically isolates the field plate from the first and second sidewalls.

17. The method of claim 16, further including forming a doped region in the epitaxial layer, the doped region extending from the surface into the epitaxial layer a distance that is less than a distance the trench extends into the epitaxial layer.

18. The method of claim 17, further including forming a gate connect structure over the epitaxial layer.

19. The method of claim 18, wherein the gate connect structure comprises one of a layer of doped polysilicon or a multi-layer structure having a silicide layer between a plurality of doped polysilicon layers.

20. The method of claim 17, further including:

forming a layer of dielectric material over the epitaxial layer and the trench;

forming an opening in the layer of dielectric material that is over the epitaxial layer to expose the conductive plug in the second trench region; and

forming a contact to the conductive plug in the second trench region.