Optically transparent wires for secure circuits and methods of making same

• US 8,207,609 B2
• Filed: 08/01/2011
• Issued: 06/26/2012
• Est. Priority Date: 05/05/2008
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Ayotte, Stephen Peter, Gambino, Jeffrey Peter, Sullivan, Timothy Dooling, Watson, Kimball M.
• Primary Examiner(s): Stark, Jarrett
• Assistant Examiner(s): TOBERGTE, NICHOLAS J
• Application Number:
  US13/195,255
• Publication Number:
  US 20110284280A1
• Time in Patent Office: 330 Days
• Field of Search: 257/749, 438/4, 438/7, 438/16, 438/609
• US Class Current: 257/749
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76867 characterized by methods of formation other than PVD, CVD or deposition from a liquids PVD H01L21/2855; CVD H01L21/28556; deposition from liquids H01L21/288
• CPC Class Codes: H01L 21/76888 By rendering at least a portion of the conductor non conductive, e.g. oxidation
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/53214 the principal metal being aluminium
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53257 the principal metal being a refractory metal
• CPC Class Codes: H01L 23/57 Protection from inspection, reverse engineering or tampering
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A structure and a method. The method includes: forming a dielectric layer on a substrate; forming electrically conductive first and second wires in the dielectric layer, top surfaces of the first and second wires coplanar with a top surface of the dielectric layer; and either (i) forming an electrically conductive third wire on the top surface of the dielectric layer, and over the top surfaces of the first and second wires, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy or (ii) forming an electrically conductive third wire between the top surface of the dielectric layer and the substrate, the third wire electrically contacting each of the first and second wires, the third wire not detectable by optical microscopy.

Claims

1. A structure, comprising:

a dielectric layer on an integrated circuit substrate said substrate including semiconductor devices, said dielectric layer having a bottom surface closet to said substrate and an opposite top surface furthest from said substrate;

electrically conductive first and second wires in said dielectric layer, top surfaces of said first and second wires coplanar with a top surface of said dielectric layer; and

an electrically conductive and patterned third wire on said top surface of said dielectric layer and on said top surfaces of said first and second wires, said third wire electrically contacting each of said first and second wires, said third wire not detectable by optical microscopy.

2. The structure of claim 1, wherein said third wire abuts said top surface of said first wire and said top surface of said second wire.

3. The structure of claim 1, wherein said first wire includes an electrically conductive first diffusion barrier layer and said second wire includes an electrically conductive second diffusion barrier layer, top surfaces of said first and second wires being coextensive with respective top surfaces of said first and second diffusion barrier layers and wherein said third wire abuts said top surfaces of said first and second diffusion barrier layers.

4. The structure of claim 1, wherein a combination of a material of said third wire and a thickness of said third wire render said third wire transparent to light having a wavelength between about 400 nm and about 700 nm.

5. The structure of claim 1, wherein said third wire has a thickness of between about 2 nm and about 10 nm.

6. The structure of claim 1, wherein (i) said third wire comprises a material selected from the group consisting of aluminum, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, chromium and combinations thereof and (ii) said each of first and second wires include copper.

7. A structure, comprising:

a dielectric layer on an integrated circuit substrate, said substrate including semiconductor devices, said dielectric layer having a bottom surface closet to said substrate and an opposite top surface furthest from said substrate;

an electrically conductive first and second wires in said dielectric layer, top surfaces of said first and second wires coplanar with a top surface of said dielectric layer; and

an electrically conductive and patterned third wire, said third wire formed in said dielectric layer, said third wire electrically contacting each of said first and second wires, said third wire not detectable by optical microscopy.

8. The structure of claim 7, wherein said third wire abuts said first wire and said second wire.

9. The structure of claim 7, wherein said first wire includes an electrically conductive first diffusion barrier layer and said second wire includes an electrically conductive second diffusion barrier layer, top surfaces of said first and second wires being coextensive with respective top surfaces of said first and second diffusion barrier layers and wherein said third wire abuts said first and second diffusion barrier layers.

10. The structure of claim 7, wherein a combination of a material of said third wire and a thickness of said third wire render said third wire transparent to light having a wavelength between about 400 nm and about 700 nm.

11. The structure of claim 7, wherein said third wire has a thickness of between about 2 nm and about 10 nm.

12. The structure of claim 7, wherein (i) said third wire comprises a material selected from the group consisting of tungsten, titanium, copper and combinations thereof and (ii) each of said first and second wires include copper.

13. A structure, comprising:

a dielectric layer on substrate;

electrically conductive first and second wires in said dielectric layer, top surfaces of said first and second wires coplanar with a top surface of said dielectric layer;

an electrically conductive third wire on said top surface of said dielectric layer and over said top surfaces of said first and second wires, said third wire electrically contacting each of said first and second wires, said third wire not detectable by optical microscopy; and

wherein said first wire includes an electrically conductive first diffusion barrier layer and said second wire includes an electrically conductive second diffusion barrier layer, top surfaces of said first and second wires being coextensive with respective top surfaces of said first and second diffusion barrier layers and wherein said third wire abuts said top surfaces of said first and second diffusion barrier layers.

14. A structure, comprising:

a dielectric layer on a substrate;

an electrically conductive first and second wires in said dielectric layer, top surfaces of said first and second wires coplanar with a top surface of said dielectric layer;

an electrically conductive third wire between said top surface of said dielectric layer and said substrate, said third wire electrically contacting each of said first and second wires, said third wire not detectable by optical microscopy; and

wherein said first wire includes an electrically conductive first diffusion barrier layer and said second wire includes an electrically conductive second diffusion barrier layer, top surfaces of said first and second wires being coextensive with respective top surfaces of said first and second diffusion barrier layers and wherein said third wire abuts said top surfaces of said first and second diffusion barrier layers.