Logic circuit and semiconductor device

• US 8,207,756 B2
• Filed: 10/26/2010
• Issued: 06/26/2012
• Est. Priority Date: 10/30/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Shionoiri, Yutaka, Kobayashi, Hidetomo
• Primary Examiner(s): Crawford, Jason M
• Application Number:
  US12/912,397
• Publication Number:
  US 20110102018A1
• Time in Patent Office: 609 Days
• Field of Search: 326/21, 326/93, 326/95, 326/98, 326/104, 326/114, 326/120
• US Class Current: 326/98
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 19/096 Synchronous circuits, i.e. using clock signals H03K19/01728, H03K19/01855 take precedence
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5×10¹⁹ (atoms/cm³) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.

Claims

1. A logic circuit including a first period during which a clock signal is input and a second period during which the clock signal is not input, comprising:

a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over the second period,

wherein a channel formation region of the transistor is formed using an oxide semiconductor in which a hydrogen concentration is 5×

10¹⁹ (atoms/cm³) or lower, and

wherein the oxide semiconductor comprises a crystal, a c-axis of which is in a direction perpendicular to a surface of the oxide semiconductor.

2. A semiconductor device comprising the logic circuit according to claim 1, and an external circuit which is configured to operate the logic circuit.

3. The logic circuit according to claim 1, wherein the crystal exists in an amorphous oxide semiconductor.

4. The logic circuit according to claim 1, wherein a grain diameter of the crystal is greater than or equal to 1 nm and less than or equal to 20 nm.

5. A logic circuit including a first period during which an enable signal is at a high level and a second period during which the enable signal is at a low level, comprising:

an AND gate, wherein a first input terminal of the AND gate is electrically connected to an enable signal line, and a second input terminal of the AND gate is electrically connected to a clock signal line; and

a flip-flop, wherein a first input terminal of the flip-flop is electrically connected to a data signal line, and a second input terminal of the flip-flop is electrically connected to an output terminal of the AND gate,

wherein the flip-flop includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over the second period,

wherein a channel formation region of the transistor is formed using an oxide semiconductor in which a hydrogen concentration is 5×

10¹⁹ (atoms/cm³) or lower, and

wherein the oxide semiconductor comprises a crystal, a c-axis of which is in a direction perpendicular to a surface of the oxide semiconductor.

6. The logic circuit according to claim 5,

wherein the AND gate comprises:

a first p-channel transistor, wherein;

a gate terminal of the first p-channel transistor is electrically connected to the enable signal line; and

a first terminal of the first p-channel transistor is electrically connected to a high power supply potential line;

a first n-channel transistor, wherein;

a gate terminal of the first n-channel transistor is electrically connected to the enable signal line and the gate terminal of the first p-channel transistor; and

a first terminal of the first n-channel transistor is electrically connected to a second terminal of the first p-channel transistor;

a second n-channel transistor, wherein;

a gate terminal of the second n-channel transistor is electrically connected to the clock signal line;

a first terminal of the second n-channel transistor is electrically connected to a second terminal of the first n-channel transistor; and

a second terminal of the second n-channel transistor is electrically connected to a low power supply potential line;

a second p-channel transistor, wherein;

a gate terminal of the second p-channel transistor is electrically connected to the clock signal line and the gate terminal of the second n-channel transistor;

a first terminal of the second p-channel transistor is electrically connected to the high power supply potential line; and

a second terminal of the second p-channel transistor is electrically connected to the second terminal of the first p-channel transistor and the first terminal of the first n-channel transistor;

a third p-channel transistor, wherein;

a gate terminal of the third p-channel transistor is electrically connected to the second terminal of the first p-channel transistor, the first terminal of the first n-channel transistor, and the second terminal of the second p-channel transistor;

a first terminal of the third p-channel transistor is electrically connected to the high power supply potential line; and

a second terminal of the third p-channel transistor is electrically connected to the second input terminal of the flip-flop; and

a third n-channel transistor, wherein;

a gate terminal of the third n-channel transistor is electrically connected to the second terminal of the first p-channel transistor, the first terminal of the first n-channel transistor, the second terminal of the second p-channel transistor, and the gate terminal of the third p-channel transistor;

a first terminal of the third n-channel transistor is electrically connected to the second input terminal of the flip-flop and the second terminal of the third p-channel transistor; and

a second terminal of the third n-channel transistor is electrically connected to the low power supply potential line.

7. The logic circuit according to claim 5,

wherein the AND gate comprises:

a first n-channel transistor, wherein a gate terminal and a first terminal of the first n-channel transistor are electrically connected to a high power supply potential line;

a second n-channel transistor, wherein a gate terminal of the second n-channel transistor is electrically connected to the enable signal line, and a first terminal of the second n-channel transistor is electrically connected to a second terminal of the first re-channel transistor;

a third n-channel transistor, wherein;

a gate terminal of the third n-channel transistor is electrically connected to the clock signal line;

a first terminal of the third n-channel transistor is electrically connected to a second terminal of the second re-channel transistor; and

a second terminal of the third n-channel transistor is electrically connected to a low power supply potential line;

a fourth n-channel transistor, wherein;

a gate terminal and a first terminal of the fourth n-channel transistor are electrically connected to the high power supply potential line; and

a second terminal of the fourth n-channel transistor is electrically connected to the second input terminal of the flip-flop; and

a fifth n-channel transistor, wherein;

a gate terminal of the fifth n-channel transistor is electrically connected to the second terminal of the first n-channel transistor and the first terminal of the second n-channel transistor;

a first terminal of the fifth n-channel transistor is electrically connected to the second input terminal of the flip-flop and the second terminal of the fourth n-channel transistor; and

a second terminal of the fifth n-channel transistor is electrically connected to the low power supply potential line.

8. The logic circuit according to claim 5, wherein the flip-flop is a delay-type flip-flop.

9. A semiconductor device comprising the logic circuit according to claim 5, and an external circuit which is configured to operate the logic circuit.

10. The logic circuit according to claim 5, wherein the crystal exists in an amorphous oxide semiconductor.

11. The logic circuit according to claim 5, wherein a grain diameter of the crystal is greater than or equal to 1 nm and less than or equal to 20 nm.

12. A logic circuit including a first period during which an enable signal is at a low level and a second period during which the enable signal is at a high level, comprising:

a NOR gate, wherein a first input terminal of the NOR gate is electrically connected to an enable signal line, and a second input terminal of the NOR gate is electrically connected to an inverted clock signal line; and

a flip-flop, wherein a first input terminal of the flip-flop is electrically connected to a data signal line, and a second input terminal of the flip-flop is electrically connected to an output terminal of the NOR gate,

wherein the flip-flop includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over the second period,

wherein a channel formation region of the transistor is formed using an oxide semiconductor in which a hydrogen concentration is 5×

10¹⁹ (atoms/cm³) or lower, and

wherein the oxide semiconductor comprises a crystal, a c-axis of which is in a direction perpendicular to a surface of the oxide semiconductor.

13. The logic circuit according to claim 12,

wherein the NOR gate comprises:

a first p-channel transistor, wherein a gate terminal of the first p-channel transistor is electrically connected to the enable signal line, and a first terminal of the first p-channel transistor is electrically connected to a high power supply potential line;

a second p-channel transistor, wherein;

a gate terminal of the second p-channel transistor is electrically connected to the inverted clock signal line;

a first terminal of the second p-channel transistor is electrically connected to a second terminal of the first p-channel transistor; and

a second terminal of the second p-channel transistor is electrically connected to the second input terminal of the flip-flop;

a first n-channel transistor, wherein;

a gate terminal of the first n-channel transistor is electrically connected to the inverted clock signal line;

a first terminal of the first n-channel transistor is electrically connected to the second input terminal of the flip-flop and the second terminal of the second p-channel transistor; and

a second terminal of the first n-channel transistor is electrically connected to a low power supply potential line; and

a second n-channel transistor, wherein;

a gate terminal of the second n-channel transistor is electrically connected to the enable signal line and the gate terminal of the first p-channel transistor;

a first terminal of the second n-channel transistor is electrically connected to the second input terminal of the flip-flop, the second terminal of the second p-channel transistor, and the first terminal of the first n-channel transistor; and

a second terminal of the second n-channel transistor is electrically connected to the low power supply potential line.

14. The logic circuit according to claim 12,

wherein the NOR gate comprises:

a first n-channel transistor, wherein a gate terminal and a first terminal of the first n-channel transistor are electrically connected to a high power supply potential line, and a second terminal of the first n-channel transistor is electrically connected to the second input terminal of the flip-flop;

a second n-channel transistor, wherein;

a gate terminal of the second n-channel transistor is electrically connected to the inverted clock signal line;

a first terminal of the second n-channel transistor is electrically connected to the second input terminal of the flip-flop and the second terminal of the first n-channel transistor; and

a second terminal of the second n-channel transistor is electrically connected to a low power supply potential line; and

a third n-channel transistor, wherein;

a gate terminal of the third n-channel transistor is electrically connected to the enable signal line;

a first terminal of the third n-channel transistor is electrically connected to the second input terminal of the flip-flop, the second terminal of the first n-channel transistor, and the first terminal of the second n-channel transistor; and

a second terminal of the third n-channel transistor is electrically connected to the low power supply potential line.

15. The logic circuit according to claim 12, wherein the flip-flop is a delay-type flip-flop.

16. A semiconductor device comprising the logic circuit according to claim 12, and an external circuit which is configured to operate the logic circuit.

17. The logic circuit according to claim 12, wherein the crystal exists in an amorphous oxide semiconductor.

18. The logic circuit according to claim 12, wherein a grain diameter of the crystal is greater than or equal to 1 nm and less than or equal to 20 nm.

19. A logic circuit including a first period during which an enable signal is at a high level and a second period during which the enable signal is at a low level, comprising:

a latch, wherein a first input terminal of the latch is electrically connected to an enable signal line, and a second input terminal of the latch is electrically connected to an inverted clock signal line; and

a flip-flop, wherein a first input terminal of the flip-flop is electrically connected to a data signal line, and a second input terminal of the flip-flop is electrically connected to an output terminal of the latch,

wherein the flip-flop includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal,

wherein a channel formation region of the transistor is formed using an oxide semiconductor in which a hydrogen concentration is 5×

10¹⁹ (atoms/cm³) or lower, and

wherein the oxide semiconductor comprises a crystal, a c-axis of which is in a direction perpendicular to a surface of the oxide semiconductor.

20. The logic circuit according to claim 19,

wherein the latch comprises:

a transistor for latch, wherein a gate terminal of the transistor is electrically connected to the enable signal line, and a first terminal of the transistor is electrically connected to the inverted clock signal line;

a first inverter, wherein an input terminal of the first inverter is electrically connected to a second terminal of the transistor for latch, and an output terminal of the first inverter is electrically connected to the second input terminal of the flip-flop; and

a second inverter, wherein an input terminal of the second inverter is electrically connected to the second input terminal of the flip-flop and the output terminal of the first inverter, and an output terminal of the second inverter is electrically connected to the second terminal of the transistor for latch and the input terminal of the first inverter.

21. The logic circuit according to claim 20,

wherein the first inverter comprises:

a first p-channel transistor, wherein;

a gate terminal of the first p-channel transistor is electrically connected to the second terminal of the transistor for latch;

a first terminal of the first p-channel transistor is electrically connected to a high power supply potential line; and

a second terminal of the first p-channel transistor is electrically connected to the second input terminal of the flip-flop; and

a first n-channel transistor, wherein;

a gate terminal of the first n-channel transistor is electrically connected to the second terminal of the transistor for latch and the gate terminal of the first p-channel transistor;

a first terminal of the first n-channel transistor is electrically connected to the second input terminal of the flip-flop and the second terminal of the first p-channel transistor; and

a second terminal of the first re-channel transistor is electrically connected to a low power supply potential line, and

wherein the second inverter comprising;

a second p-channel transistor, wherein;

a gate terminal of the second p-channel transistor is electrically connected to the second input terminal of the flip-flop, the second terminal of the first p-channel transistor, and the first terminal of the first re-channel transistor;

a first terminal of the second p-channel transistor is electrically connected to the high power supply potential line; and

a second terminal of the second p-channel transistor is electrically connected to the second terminal of the transistor for latch, the gate terminal of the first p-channel transistor, and the gate terminal of the first n-channel transistor; and

a second n-channel transistor, wherein;

a gate terminal of the second n-channel transistor is electrically connected to the second input terminal of the flip-flop, the second terminal of the first p-channel transistor, the first terminal of the first n-channel transistor, and the gate terminal of the second p-channel transistor;

a first terminal of the second n-channel transistor is electrically connected to the second terminal of the transistor for latch, the gate terminal of the first p-channel transistor, the gate terminal of the first n-channel transistor, and the second terminal of the second p-channel transistor; and

a second terminal of the second n-channel transistor is electrically connected to the low power supply potential line.

22. The logic circuit according to claim 20,

wherein the first inverter comprises:

a first n-channel transistor, wherein;

a gate terminal and a first terminal of the first n-channel transistor are electrically connected to a high power supply potential line; and

a second terminal of the first n-channel transistor is electrically connected to the second input terminal of the flip-flop; and

a second n-channel transistor, wherein;

a gate terminal of the second n-channel transistor is electrically connected to the second terminal of the transistor for latch;

a first terminal of the second n-channel transistor is electrically connected to the second input terminal of the flip-flop and the second terminal of the first n-channel transistor; and

a second terminal of the second n-channel transistor is electrically connected to a low power supply potential line, and

wherein the second inverter comprising;

a third n-channel transistor, wherein;

a gate terminal and a first terminal of the third n-channel transistor are electrically connected to the high power supply potential line; and

a second terminal of the third n-channel transistor is electrically connected to the second terminal of the transistor for latch, and the gate terminal of the second re-channel transistor; and

a fourth n-channel transistor, wherein;

a gate terminal of the fourth n-channel transistor is electrically connected to the second input terminal of the flip-flop, the second terminal of the first n-channel transistor, and the first terminal of the second re-channel transistor;

a first terminal of the fourth n-channel transistor is electrically connected to the second terminal of the transistor for latch, the gate terminal of the second n-channel transistor, and the second terminal of the third n-channel transistor; and

a second terminal of the fourth n-channel transistor is electrically connected to the low power supply potential line.

23. The logic circuit according to claim 19, wherein the flip-flop is a delay-type flip-flop.

24. A semiconductor device comprising the logic circuit according to claim 19, and an external circuit which is configured to operate the logic circuit.

25. The logic circuit according to claim 19, wherein the crystal exists in an amorphous oxide semiconductor.

26. The logic circuit according to claim 19, wherein a grain diameter of the crystal is greater than or equal to 1 nm and less than or equal to 20 nm.