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Logic circuit and semiconductor device

  • US 8,207,756 B2
  • Filed: 10/26/2010
  • Issued: 06/26/2012
  • Est. Priority Date: 10/30/2009
  • Status: Active Grant
First Claim
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1. A logic circuit including a first period during which a clock signal is input and a second period during which the clock signal is not input, comprising:

  • a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over the second period,wherein a channel formation region of the transistor is formed using an oxide semiconductor in which a hydrogen concentration is 5×

    1019 (atoms/cm3) or lower, andwherein the oxide semiconductor comprises a crystal, a c-axis of which is in a direction perpendicular to a surface of the oxide semiconductor.

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