Method and apparatus for MOSFET drain-source leakage reduction

• US 8,207,784 B2
• Filed: 02/12/2009
• Issued: 06/26/2012
• Est. Priority Date: 02/12/2008
• Status: Active Grant

• Current Assignee: Semi Solutions LLC
• Original Assignee: Semi Solutions LLC
• Inventors: Tsividis, Yannis
• Primary Examiner(s): TRA, ANH QUAN
• Application Number:
  US12/370,248
• Publication Number:
  US 20090201081A1
• Time in Patent Office: 1,230 Days
• Field of Search: 327/534, 327/544
• US Class Current: 327/534
• CPC Class Codes: G05F 3/205 Substrate bias-voltage generators for static stores G11C5/146
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits

Abstract

A method and apparatus is taught for reducing drain-source leakage in MOS circuits. In an exemplary CMOS inverter, a first transistor causes the body of an affected transistor to be at a first body potential. A second transistor brings the body potential of the affected transistor to a second body potential by providing an accurate body voltage from a body voltage source. Exemplary body bias voltage sources are further described that can drive one or more gate transistors of different gate circuits.

Claims

1. A leakage control circuit for a logic gate, comprising:

a logic gate comprising a first N-type metal-oxide semiconductor (NMOS) transistor and a first P-type metal-oxide semiconductor (PMOS) transistor, each transistor having a body terminal, a drain terminal, a source terminal, and a gate terminal, and where at least the gate terminal of the first PMOS transistor and the gate terminal of the NMOS transistor are connected; and

a control circuit coupled to said logic gate via any of said first NMOS transistor and said PMOS transistor, said control circuit comprising;

a first metal-oxide semiconductor (MOS) transistor having a drain terminal connected to the body terminal of any of said first NMOS transistor and said first PMOS transistor to bring said body terminal to a first reference potential, and a gate terminal of said first MOS transistor connected to the drain terminal of any of said first NMOS transistor and said first PMOS transistor, wherein a body terminal of the first MOS transistor is grounded; and

a second MOS transistor having a source terminal connected to said body terminal of any of said first NMOS transistor and said first PMOS transistor to bring said body terminal to a second reference potential, and a gate terminal of said second MOS transistor connected to the gate terminal of any of said first NMOS transistor and said first PMOS transistor, said second reference potential provided by a positive body bias voltage supply connected to a drain terminal of the second MOS transistor and having a potential higher than a common ground for said NMOS transistor or a bias voltage supply having a potential lower than a common supply voltage of said PMOS transistor that provides a bias voltage to establish a predetermined current enhancement ratio (CER), wherein a body terminal of the second MOS transistor is grounded.

2. The circuit of claim 1, wherein said CER expresses a ratio between a current of said drain of any of said first NMOS transistor and said first PMOS transistor with body bias to a current of said drain of any of said first NMOS transistor and said PMOS transistor without body bias.

3. The circuit of claim 1, wherein said CER expresses a ratio of width over length of a reference current device and a width over length of an adaptive body bias device, multiplied by a ratio of width over length of a first transistor of a current mirror circuit of said body bias voltage supply and a second transistor of a current mirror circuit of said body bias voltage supply.

4. The circuit of claim 1, wherein the logic gate is any of an inverter, NAND, NOR, AND, OR, XOR, NXOR, AND-OR, and OR-AND.

5. A circuit, comprising:

a first metal-oxide semiconductor (MOS) transistor of a logic gate having a gate terminal, a source terminal, a drain terminal, and a body terminal, wherein at least the gate terminal of the first MOS transistor and a gate terminal of a second MOS transistor of the logic gate are connected, the second MOS transistor having an opposite polarity of that of the first MOS transistor; and

a control circuit coupled to said first MOS transistor, said control circuit comprising;

a third MOS transistor having a drain terminal connected to said body terminal of said first MOS transistor to bring said body terminal to a first reference potential supplied by a reference source connected to a source terminal of said third MOS transistor, and a gate terminal of said third MOS transistor connected to said drain terminal of said first MOS transistor, wherein a body terminal of the first MOS transistor is grounded; and

a fourth MOS transistor having a source terminal coupled to said body terminal of said first MOS transistor to bring said body terminal of said first MOS transistor to a second reference potential, and a gate terminal of said fourth MOS transistor connected to said gate terminal said first NMOS transistor, said second reference potential provided by a body bias voltage supply, connected to a drain terminal of the second MOS transistor, to establish a predetermined current enhancement ratio (CER), wherein a body terminal of the second MOS transistor is grounded;

said control circuit controlling leakage of said first MOS device.

6. The circuit of claim 5, wherein said CER expresses a ratio between a current of said drain of said second MOS transistor with body bias to a current of said drain of said second MOS transistor without body bias.

7. The circuit of claim 5, wherein said second MOS transistor is any of a P-type MOS (PMOS) transistor and an N-type MOS (NMOS) transistor.

8. The circuit of claim 5, wherein said CER expresses a ratio of width over length of a reference current transistor and a width over length of the first MOS transistor, multiplied by a ratio of width over length of a first transistor of a current mirror circuit of said body bias voltage supply and a second transistor of said current mirror circuit of said body bias voltage supply.

9. The circuit of claim 5, wherein said MOS device comprises a portion of a logic gate.

10. The circuit of claim 9, wherein said logic gate comprises any of an inverter, NAND, NOR, AND, OR, XOR, NXOR, AND-OR, and OR-AND.

11. A body voltage control circuit for controlling leakage of a metal-oxide semiconductor (MOS) transistor of a logic gate, comprising:

a first MOS transistor having a drain terminal connected to a body terminal of the MOS transistor to bring said body terminal of the MOS transistor to a first reference potential, and a gate terminal of said first MOS transistor connected to the drain terminal of said MOS transistor, wherein a body terminal of the MOS transistor is grounded;

a second MOS transistor having a source terminal connected to said body terminal of the MOS transistor of a logic gate to bring said body terminal of the MOS transistor of a logic gate to a second reference potential from a body bias voltage supply, and a gate terminal of said second MOS transistor connected to the gate terminal said MOS transistor of a logic gate, wherein a body terminal of the second MOS transistor is grounded; and

the body bias voltage supply connected to the drain of said second MOS transistor to establish a predetermined current enhancement ratio (CER).

12. The circuit of claim 11, wherein said CER expresses a ratio between a current of said drain of the MOS transistor with body bias to a current of said drain of the MOS transistor without body bias.

13. The circuit of claim 11, wherein the MOS transistor comprises any of a P-type MOS (PMOS) transistor and an N-type MOS (NMOS) transistor.

14. The circuit of claim 11, wherein said CER expresses a ratio of width over length of a reference current device and a width over length of an adaptive body bias device, multiplied by a ratio of width over length of a first transistor of a current mirror circuit of said body bias voltage supply and a second transistor of a current mirror circuit of said body bias voltage supply.

15. A method of manufacturing a leakage control circuit to control leakage of a metal-oxide semiconductor (MOS) transistor of a logic gate, comprising the steps of:

forming the MOS transistor on a substrate, the MOS transistor having a gate terminal, a drain terminal, a source terminal, and a body terminal;

forming a first MOS transistor having a drain terminal connected to said body terminal of the MOS transistor to bring said body terminal of the MOS transistor to a first reference potential, and a gate terminal of said first MOS transistor connected to the drain terminal of said MOS transistor, wherein a body terminal of the first MOS transistor is grounded; and

forming a second MOS transistor of said logic gate having a source terminal coupled to said body terminal of the MOS transistor to bring said body terminal of the MOS transistor to a second reference potential, and a gate terminal of said first MOS transistor of said logic gate connected to the gate terminal of said MOS transistor, wherein a body terminal of the second MOS transistor is grounded;

said second reference potential provided by a body bias voltage supply connected to a drain terminal of said second MOS transistor that provides a bias voltage to establish a predetermined current enhancement ratio (CER).

16. The method of claim 15, further comprising the step of:

expressing said current enhancement ratio (CER) as a ratio between a current of said drain of the MOS transistor with body bias to a current of said drain of the MOS transistor without body bias.

17. The method of claim 15, further comprising the step of:

expressing said CER as a ratio of width over length of a reference current device and a width over length of the MOS transistor, multiplied by a ratio of width over length of a first transistor of a current mirror circuit of said body bias voltage supply and a second transistor of a current mirror circuit of said body bias voltage supply.

18. The method of claim 15, said MOS transistor of said logic gate comprising any of a P-type MOS (PMOS) transistor and an N-type MOS (NMOS) transistor.

19. A method for controlling leakage current of a MOS transistor of a logic gate, said MOS transistor comprising a gate terminal, a drain terminal, a source terminal and a body terminal, the method comprising the steps of:

supplying a first reference voltage to the body of the MOS transistor by a first MOS transistor having its drain connected to said body terminal of said MOS transistor and its gate connected to said drain terminal of said MOS transistor to bring the body terminal of the MOS transistor to a first reference potential;

supplying a second reference potential to the body of the MOS transistor by a second MOS transistor having its source connected to said body terminal of said MOS transistor and its gate connected to said gate terminal of said MOS transistor to bring the body terminal of the MOS transistor to a second reference potential; and

supplying a bias to a drain terminal of said second MOS transistor for said second reference potential to establish a predetermined current enhancement ratio (CER).

20. The method of claim 19, wherein said CER expresses a ratio between a current of said drain of the MOS transistor with body bias to a current of said drain of the MOS transistor without body bias.

21. The method of claim 19, wherein the MOS transistor comprises any of a P-type MOS (PMOS) transistor and an N-type MOS (NMOS) transistor.

22. The method of claim 19, wherein said CER expresses a ratio of width over length of a reference current device and width over length of the MOS transistor, multiplied by a ratio of width over length of a first transistor of a current mirror circuit of a body bias voltage supply and a second transistor of a current mirror circuit of said body bias voltage supply, said body bias voltage supply provided to said control circuit.