Method, device and system of generating a clock signal corresponding to a wireless video transmission

• US 8,208,068 B2
• Filed: 09/05/2007
• Issued: 06/26/2012
• Est. Priority Date: 09/06/2006
• Status: Active Grant

• Current Assignee: Amimon Limited (Vitec Group PLC)
• Original Assignee: Amimon Limited (Vitec Group PLC)
• Inventors: Elnathan, Nathan, Freundlich, Shay
• Primary Examiner(s): NATNAEL, PAULOS M
• Application Number:
  US12/310,730
• Publication Number:
  US 20100071010A1
• Time in Patent Office: 1,756 Days
• Field of Search: 348723-726, 348/500, 348/521, 348/524, 348/537, 348/547
• US Class Current: 348/500
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop
• CPC Class Codes: H04N 5/06 Generation of synchronising signals

Abstract

Some demonstrative embodiments include devices, systems and/or methods of wireless video communication. Some embodiments include a wireless video receiver to receive a wireless video transmission including data representing pixels of a video frame and a synchronization signal indicative of a beginning of the video frame, the wireless receiver including a clock generator to generate a pixel clock signal synchronized to the synchronization signal, wherein a clock rate of the pixel clock signal corresponds to a pixel rate of the pixels. Other embodiments are described and claimed.

Claims

1. A wireless video receiver to receive a wireless video transmission including data associated with pixels of a video frame and a synchronization signal indicative of a beginning of said video frame, said wireless receiver comprising:

a multistage clock generator to generate a pixel clock signal at least partially based on the synchronization signal;

wherein said clock generator comprises;

(1) a first clock generation module to generate an intermediate clock signal at least partially based on the synchronization signal, and wherein an intermediate clock rate of said intermediate clock signal is lower than the pixel rate; and

(2) a second clock generation module to generate the pixel clock signal at least partially based on the intermediate clock signal; and

wherein said first clock generation module comprises a digital phase-locked loop and said second clock generation module comprises an analog phase-locked loop.

2. The receiver of claim 1, wherein the clock rate of the pixel clock signal is at least ten times greater than said intermediate clock rate.

3. The receiver of claim 1, wherein the clock rate of said pixel clock signal is at least four orders of magnitude greater than said intermediate clock rate.

4. The receiver of claim 1, wherein said first clock generation module comprises:

a counter to generate said intermediate clock signal based on a value of said counter;

an offset register to maintain an offset value; and

an adder to add said offset value to the value of said counter at a system clock rate of a system clock of said receiver.

5. The receiver of claim 4, wherein said clock generator is to adjust the offset value maintained by the offset register based on at least one of said intermediate clock signal and said pixel clock signal.

6. The receiver of claim 1, wherein said wireless video receiver is capable of generating one or more video control signals based on said pixel clock signal, said video control signals comprising at least one of a horizontal-synchronization signal, a vertical synchronization signal, and a synchronization-on-green signal.

7. A wireless video communication system comprising:

a wireless video transmitter to transmit a wireless video transmission including data representing pixels of a video frame and a synchronization signal indicative of a beginning of said video frame; and

a wireless video receiver to receive said wireless video transmission, said receiver comprising a multistage clock generator to generate a pixel clock signal at least partially synchronized to said synchronization signal;

wherein a clock rate of said pixel clock signal at least partially corresponds to a pixel rate of said pixels, and wherein said clock generator comprises a first clock generation module to generate an intermediate clock signal at least partially synchronized to said synchronization signal, such that an intermediate clock rate of said intermediate clock signal is lower than said pixel rate;

further comprising a second clock generation module to generate said pixel clock signal based at least partially on said intermediate clock signal; and

wherein said first clock generation module comprises a digital phase-locked loop and said second clock generation module comprises an analog phase-locked loop.

8. The system according to claim 7, wherein the clock rate of said pixel clock signal is at least ten times higher than said intermediate clock rate.

9. The system of claim 7, wherein said first clock generation module comprises:

a counter to generate said intermediate clock signal based on a value of said counter;

an offset register to maintain an offset value; and

an adder to add said offset value to the value of said counter at a system clock rate of a system clock of said receiver.

10. The system of claim 7, wherein said clock generator is to adjust the offset value maintained by the offset register based on at least one of said intermediate clock signal and said pixel clock signal.

11. The system of claim 7, wherein said wireless video receiver is capable of generating one or more video control signals based on said pixel clock signal, said video control signals comprising at least one of a horizontal-synchronization signal, a vertical synchronization signal, and a synchronization-on-green signal.

12. A method of wireless video communication, the method comprising:

receiving a wireless video transmission including data representing pixels of a video frame and a synchronization signal indicative of a beginning of said video frame; and

generating a pixel clock signal synchronized at least partially to said synchronization signal, wherein a clock rate of said pixel clock signal corresponds to a pixel rate of said pixels, and wherein generating said pixel clock comprises two stages;

wherein generating a pixel clock includes generating an intermediate clock signal at least partially synchronized to said synchronization signal, and generating said pixel clock signal based on said intermediate clock signal; and

wherein generating the intermediate clock signal comprises;

generating said intermediate clock signal based on a value of a counter;

maintaining an offset value; and

adding said offset value to the value of said counter at a system clock rate of a system clock.