Integrated circuit self aligned 3D memory array and manufacturing method

• US 8,208,279 B2
• Filed: 01/25/2010
• Issued: 06/26/2012
• Est. Priority Date: 03/03/2009
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lue, Hang-Ting
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US12/692,798
• Publication Number:
  US 20100226195A1
• Time in Patent Office: 883 Days
• Field of Search: 365/46, 365/100
• US Class Current: 365/63
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as bit lines which can be coupled through decoding circuits to sense amplifiers. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. The conductive lines conform to the surface of the stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines. The memory elements are programmable, like the anti-fuses or charge trapping structures. The 3D memory is made using only two critical masks for multiple layers.

Claims

1. A memory device, comprising:

an integrated circuit substrate;

a plurality of stacks of conductive strips, the stacks being ridge-shaped and including at least two conductive strips separated by insulating material;

a plurality of conductive lines arranged orthogonally over, and having surfaces conformal with, the plurality of stacks, defining a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and conductive lines; and

memory elements in the interface regions, which establish a 3D array of memory cells accessible via the plurality of conductive strips and the plurality of conductive lines.

2. The memory device of claim 1, including

decoding circuits coupled to the conductive strips in the plurality of stacks and to the plurality of conductive lines for accessing the memory cells.

3. The memory device of claim 1, wherein the memory elements comprise an anti-fuse.

4. The memory device of claim 1, wherein the memory elements comprise a charge storage structure.

5. The memory device of claim 1, wherein the memory cells comprise buried channel charge storage transistors.

6. The memory device of claim 1, wherein the plurality conductive strips in the stacks comprise a doped semiconductor.

7. The memory device of claim 1, wherein the plurality of conductive lines comprise a doped semiconductor.

8. The memory device of claim 1, wherein said memory elements comprise portions of a common layer of memory material between the plurality of conductive lines and the plurality of stacks.

9. The memory device of claim 1, including a tunneling layer, a charge trapping layer and a blocking layer between the plurality of conductive lines and the plurality of stacks, and wherein said tunneling layer, charge trapping layer and blocking layer in combination form said memory elements in said interface regions.

10. A memory device, comprising:

an integrated circuit substrate;

a plurality of stacks of conductive strips, the stacks being ridge-shaped and including at least two conductive strips separated by insulating material;

a plurality of conductive lines arranged orthogonally over, and having surfaces conformal with, the plurality of stacks, defining a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and conductive lines;

a layer of programmable resistive memory material between the plurality of conductive lines and the plurality of stacks, which establishes a 3D array of memory cells accessible via the plurality of conductive strips and the plurality of conductive lines;

a row decoder coupled to the plurality of conductive lines; and

a plane and column decoder coupled to the conductive strips in the plurality of stacks.

11. The memory device of claim 10, wherein the programmable resistance material comprises an anti-fuse material.

12. The memory device of claim 10, wherein the programmable resistance material comprises silicon oxide and has a thickness less than 5 nanometers.

13. The memory device of claim 10, wherein the plurality of conductive strips in the stacks comprise a doped semiconductor having a first conductivity type and the plurality of conductive lines comprise a doped semiconductor material having a second conductivity type establishing a p-n junction in said interfaces.

14. The memory device of claim 10, wherein the column and plane decoder includes sets of local select transistors arranged to connect selected planes of conductive strips orthogonal to said stacks, to corresponding sets of bit lines, and column select transistors arranged to connect selected bit lines to bias or sensing circuits.

15. The memory device of claim 10, wherein the column and plane decoder includes sets of local select transistors arranged to connect selected planes of conductive strips parallel to said stacks to corresponding sets of bit lines, and column select transistors arranged to connect selected bit lines to bias or sensing circuits.

16. A memory device, comprising:

an integrated circuit substrate;

a plurality of stacks of semiconductor strips, the stacks being ridge-shaped and including at least two semiconductor strips separated by insulating material;

a plurality of conductive lines arranged orthogonally over, and having surfaces conformal with, the plurality of stacks, defining a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor strips on the plurality of stacks and conductive lines;

charge trapping structures in the interface regions between the plurality of conductive lines and the side surfaces of the semiconductor strips on the plurality of stacks, which establishes a 3D NAND array of charge trapping memory transistors accessible via the plurality of semiconductor strips and the plurality of conductive lines.

17. The memory device of claim 16, including

a reference source coupled to the plurality of semiconductor strips in the plurality of stacks at a first end;

a row decoder coupled to the plurality of conductive lines; and

a plane and column decoder coupled to the semiconductor strips in the plurality of stacks at a second end.

18. The memory device of claim 16, wherein the charge trapping structures in the interface regions respectively comprise a tunneling layer, a charge trapping layer and a blocking layer.

19. The memory device of claim 18, wherein the tunneling layer comprises a combination of materials arranged to establish a relatively low valence band energy level near the side surface of the semiconductor strips, and an increase in valence band energy level at a first distance of less than 2 nm from the side surface and a decrease in valence band energy at a second distance more than said first distance from the side surface.

20. The memory device of claim 18, wherein the tunneling layer comprises a layer of silicon dioxide less than 2 nm thick, a layer of silicon nitride less than 3 nm thick, and a layer of silicon dioxide less that 4 nm thick.

21. The memory device of claim 16, wherein the semiconductor strips comprise n-type silicon.

22. The memory device of claim 16, wherein the semiconductor strips consist essentially of doped, single crystal silicon.

23. The memory device of claim 16, wherein said memory transistors are buried channel transistors.

24. The memory device of claim 16, including a column and plane decoder having sets of string select transistors arranged to connect semiconductor strips in a selected stack of semiconductor strips to bit lines in planes orthogonal to said stacks and plane select transistors arranged to connect selected bit lines to bias or sensing circuits.

25. The memory device of claim 16, wherein insulating material between the semiconductor strips within a ridge shaped stack has an effective oxide thickness of about 40 nm or greater.

26. The memory device of claim 16, wherein insulating material between the semiconductor strips within a ridge shaped stack has an effective oxide thickness of 30 nm or greater.

27. A memory device, comprising:

an integrated circuit substrate;

a plurality of stacks of n-type semiconductor strips, the stacks being ridge-shaped and including at least two semiconductor strips separated by insulating material;

a plurality of p-type semiconductor lines arranged orthogonally over, and having surfaces conformal with, the plurality of stacks, defining a multi-layer array of interface regions at cross-points between side surfaces of the semiconductor strips on the plurality of stacks and the plurality of p-type semiconductor lines;

charge trapping structures in the interface regions between the plurality of conductive lines and the side surfaces of the semiconductor strips on the plurality of stacks, which establishes a 3D NAND array of charge trapping memory transistors accessible via the plurality of semiconductor strips and the plurality of conductive lines, the charge trapping structures including a tunneling dielectric structure including a composite of materials to establish an inverted U-shaped valence band energy level, a charge trapping layer and a blocking layer.

28. A method for manufacturing a memory device, comprising:

forming a plurality of layers of a first conductive material separated by insulating material, on an integrated circuit substrate;

etching the plurality of layers to define a plurality of stacks of conductive strips, the stacks being ridge-shaped and including at least two conductive strips separated by insulating material;

forming a memory layer on sides of conductive strips in the plurality of stacks, the memory layer contacting side surfaces of the plurality of conductive strips;

forming a layer of a second conductive material over and having a surface conformal with the memory layer on the plurality of stacks; and

etching the layer of second conductive material to define a plurality of conductive lines arranged orthogonally over, and having surfaces conformal with, the memory layer on the plurality of stacks, defining a 3D array of memory cells in interface regions at cross-points between side surfaces of the conductive strips on the stacks and conductive lines.

29. The method of claim 28, wherein the memory layer comprises a layer of anti-fuse material.

30. The method of claim 28, wherein the memory layer includes a multilayer charge storage structure.

31. The method of claim 30, wherein the first conductive material comprises a doped semiconductor so that the conductive strips are arranged for operation of the memory cells as buried channel charge storage transistors.

32. The method of claim 28, wherein the first conductive material comprises a doped semiconductor.

33. The method of claim 32, wherein the first conductive material comprises n-type semiconductor.

34. The method of claim 32, wherein the plurality of conductive lines comprises a doped semiconductor having a conductivity type opposite that of the first conductive material.

35. The method of claim 28, wherein the memory layer includes a tunneling layer, a charge trapping layer and a blocking layer.

36. The method of claim 28, including implanting doping material to establish source/drain terminals in the conductive strips between the plurality of conductive lines.

37. The method of claim 28, wherein insulating material between the semiconductor strips within a ridge shaped stack has an effective oxide thickness of about 40 nm or greater.

38. The method of claim 28, wherein insulating material between the semiconductor strips within a ridge shaped stack has an effective oxide thickness of 30 nm or greater.