Vertically stacked field programmable nonvolatile memory and method of fabrication

• US 8,208,282 B2
• Filed: 10/07/2010
• Issued: 06/26/2012
• Est. Priority Date: 11/16/1998
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Johnson, Mark G., Lee, Thomas H., Subramanian, Vivek, Farmwald, Paul Michael, Cleeves, James M.
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US12/899,634
• Publication Number:
  US 20110019467A1
• Time in Patent Office: 628 Days
• Field of Search: 365/115, 365/148, 365/105, 365/100, 365/175, 365/72
• US Class Current: 365/115
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/76 Array using an access device for each cell which being not a transistor and not a diode
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices

Abstract

A memory cell is provided that includes a first conductor, a second conductor, a steering element that is capable of providing substantially unidirectional current flow, and a state change element coupled in series with the steering element. The state change element is capable of retaining a programmed state, and the steering element and state change element are vertically aligned with one another. Other aspects are also provided.

Claims

1. A memory cell comprising:

a first conductor;

a second conductor;

a steering element that is capable of providing substantially unidirectional current flow; and

a state change element coupled in series with the steering element, wherein the state change element is capable of retaining a programmed state, and wherein the steering element and state change element are vertically aligned with one another.

2. The memory cell of claim 1, wherein the steering element comprises a diode.

3. The memory cell of claim 1, wherein the steering element comprises a p-n diode.

4. The memory cell of claim 1, wherein the steering element comprises a p-i-n diode.

5. The memory cell of claim 1, wherein the steering element comprises a Schottky diode.

6. The memory cell of claim 1, wherein the state change element comprises a resistance-switching element.

7. The memory cell of claim 1, wherein the state change element is capable of having a high impedance state, and a low-impedance state.

8. The memory cell of claim 1, wherein the state change element is capable of having two resistance states.

9. The memory cell of claim 1, wherein the state change element is capable of having more than two resistance states.

10. A memory array comprising a plurality of the memory cells of claim 1.

11. A memory cell comprising:

a first conductor;

a second conductor; and

a pillar comprising a steering element that is capable of providing substantially unidirectional current flow, and a state change element that is capable of retaining a programmed state.

12. The memory cell of claim 11, wherein the steering element comprises a diode.

13. The memory cell of claim 11, wherein the steering element comprises a p-n diode.

14. The memory cell of claim 11, wherein the steering element comprises a p-i-n diode.

15. The memory cell of claim 11, wherein the steering element comprises a Schottky diode.

16. The memory cell of claim 11, wherein the state change element comprises a resistance-switching element.

17. The memory cell of claim 11, wherein the state change element is capable of having a high impedance state, and a low-impedance state.

18. The memory cell of claim 11, wherein the state change element is capable of having two resistance states.

19. The memory cell of claim 11, wherein the state change element is capable of having more than two resistance states.

20. A memory array comprising a plurality of the memory cells of claim 11.