Integrated circuit embedded with non-volatile programmable memory having variable coupling and separate read/write paths

• US 8,208,299 B2
• Filed: 08/26/2010
• Issued: 06/26/2012
• Est. Priority Date: 11/14/2007
• Status: Expired due to Fees

• Current Assignee: Invensas Corporation
• Original Assignee: Invensas Corporation
• Inventors: Liu, David, Gross, John Nicholas
• Primary Examiner(s): Nguyen, Tan T.
• Application Number:
  US12/869,378
• Publication Number:
  US 20100322001A1
• Time in Patent Office: 670 Days
• Field of Search: None
• US Class Current: 365/185.03
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/47 with a floating-gate layer also being used as part of the peripheral transistor
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A multi-programmable non-volatile device is operated with a floating gate that functions as a FET gate that overlaps a portion of a source/drain region and allows for variable coupling through geometry and/or biasing conditions. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. Different source/drain regions can be used for program and read operations. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications.

Claims

1. A programmable non-volatile device situated on a substrate, the programmable device comprising:

a floating gate overlying an n-type diffusion region;

a source region coupled to a first terminal; and

a drain region coupled to a plurality of second terminals; and

wherein the drain region overlaps a sufficient portion of said gate such that a programming voltage for the device applied to said drain region can be imparted to said floating gate through areal capacitive coupling applied to said first terminal and at least a first one or more of said plurality of second terminals;

an n-channel coupling said source region and said drain region;

wherein the device is adapted so that data stored therein can be read by a read signal applied to different ones of said plurality of second terminals than is/are used for said programming voltage, such that different source/drain regions are used for read and write operations.

2. The programmable device of claim 1 wherein the device is adapted such that during a read operation only a portion of said drain region receives a read voltage.

3. The programmable device of claim 1 wherein the device is adapted such that a portion or all of said drain region can be biased during a program operation to vary an amount of information stored in the device.

4. The programmable device of claim 1 wherein said floating gate can be erased.

5. The programmable device of claim 4 wherein said device can be re-programmed.

6. The programmable device of claim 4 wherein said floating gate is eraseable by an erase voltage applied to said source region.

7. The programmable device of claim 1 wherein said device is part of a programmable array embedded with at least one of a separate logic circuit or a memory circuit in an integrated circuit.

8. The programmable device of claim 7 wherein said device is associated with at least one a data encryption circuit;

a reference trimming circuit;

a manufacturing ID;

or a security ID.

9. The programmable device of claim 1, wherein said capacitive coupling takes place in a first trench situated in the substrate.

10. The programmable device of claim 9, wherein a set of second trenches in said substrate are used as embedded DRAM.

11. The programmable device of claim 1, further including a second programmable device coupled in a paired latch arrangement such a datum and its compliment are stored in said paired latch.

12. The programmable device of claim 1, wherein the device is adapted to be read by a bias voltage applied to said drain region which is adjusted with time to determine a threshold voltage of said floating gate.

13. The programmable device of claim 1, wherein the device is programmed to a multi-level state by a variable programming voltage.

14. A multi-level programmable device situated on a substrate, the programmable device comprising:

a floating gate;

said floating gate being comprised of a material that includes impurities acting as charge storage sites and is used as an insulating layer for other non-programmable devices situated on the substrate;

a source region; and

a drain region comprised of a first drain region and a second drain region; and

wherein the drain region overlaps a sufficient portion of said gate such that a programming voltage for the device applied to either or both of said first drain region and second drain region can be imparted to said floating gate through capacitive coupling, such that multiple bits of data can be written by said programming voltage;

further wherein the device is adapted so that data stored therein can be read by a read signal applied differently to the device than said programming voltage, such that different source/drain regions are used for read and write operations.

15. The multi-level programmable device of claim 14, wherein the device is adapted to be read by a bias voltage applied to said drain region which is adjusted with time to determine a threshold voltage of said floating gate.

16. The multi-level programmable device of claim 14, wherein the device is programmed to a multi-level state by a variable programming voltage.

17. A method of operating a multi-level one-time programmable (MOTP) cell situated on a substrate comprising:

providing a floating gate overlying an n-type diffusion region;

wherein said floating gate is comprised of a material that is shared by at least one of an interconnect or another gate for a transistor device situated on the substrate and associated with at least one of a logic gate or a volatile memory;

providing a source region; and

providing a drain region overlapping a variable portion of said floating gate and capacitively coupled thereto;

wherein an amount of capacitive coupling can be adjusted based on at least one of altering a first number of N (N>

1) separate drain regions selected to overlap said floating gate or by altering a programming voltage level;

setting a threshold of said floating gate based on a current of channel hot electrons;

wherein said threshold can be set to more than two (2) separate distinguishable states to effectuate a multi-level storage cell;

providing a read signal applied to a different number of said separate drain regions to read said separate distinguishable states;

wherein the device is adapted so that different source/drain regions are used for read and write operations.

18. The method of claim 17, wherein the device is read by a bias voltage applied to said drain region which is adjusted with time to determine a threshold voltage of said floating gate.

19. The method of claim 17, wherein the device is programmed to a multi-level state by a variable programming voltage.

20. The method of claim 17, wherein said n-type diffusion region is formed at a same time as other n-channel logic devices on the substrate.