Method of maintaining the state of semiconductor memory having electrically floating body transistor

• US 8,208,302 B2
• Filed: 09/26/2011
• Issued: 06/26/2012
• Est. Priority Date: 11/29/2007
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto, Or-Bach, Zvi
• Primary Examiner(s): Nguyen, Tuan T.
• Application Number:
  US13/244,855
• Publication Number:
  US 20120014188A1
• Time in Patent Office: 274 Days
• Field of Search: 365/185.08, 365/185.18, 365/185.05
• US Class Current: 365/185.05
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4067 for memory cells of the bipolar type
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/4099 Dummy cell treatment; Reference voltage generators
• CPC Class Codes: G11C 11/565 using capacitive charge storage elements
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/1004 Base region of bipolar transistors
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7455 produced by an insulated gate structure
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/00 : Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/10 : DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.

Claims

1. A method of maintaining a state of a memory cell without interrupting access to said memory cell, said method comprising:

applying a back bias to the cell, wherein application of said back bias to said cell results in at least two stable floating body charge levels.

2. The method of claim 1, wherein said applying comprises applying said back bias to a terminal of said cell that is not used for address selection of said cell.

3. The method of claim 1, wherein said back bias is applied as a constant positive voltage bias.

4. The method of claim 1, wherein said back bias is applied as a periodic pulse of positive voltage.

5. The method of claim 1, wherein a maximum potential that can be stored in said floating body is increased by said applying back bias to the cell, resulting in a relatively larger memory window.

6. The method of claim 1, wherein said application of back bias performs a holding operation on said cell, said method further comprises simultaneously performing a read operation on said cell at the same time that said holding operation is being performed.

7. The method of claim 1, wherein the cell is a multi-level cell, wherein said floating body is configured to indicate more than one state by storing multi-bits, said method further comprising monitoring cell current of said cell to determine a state of said cell.

8. A method of operating a memory array having rows and columns of memory cells assembled into an array of said memory cells, each said memory cell having a floating body region for storing data;

the method comprising;

performing a holding operation on at least all of said cells not aligned in a row or column of a selected cell; and

accessing said selected cell and performing a read or write operation on said selected cell while performing said holding operation on said at least all of said cells not aligned in a row or column of said selected cell;

wherein said holding operation results in at least two stable floating body states.

9. The method of claim 8, wherein said performing a holding operation comprises performing said holding operation on all of said cells and wherein said performing a read or write operation comprises performing a read operation on said selected cell.

10. The method of claim 8, wherein said holding operation is performed by applying back bias to a terminal not used for memory address selection.

11. The method of claim 10, wherein said terminal is segmented to allow independent control of the applied back bias to a selected portion of the memory array.

12. The method of claim 8, wherein said performing a holding operation comprises performing said holding operation on all of said cells except for said selected cell, and wherein said performing a read or write operation comprises performing a write “

0”

operation on said selected cell, wherein a write “

0”

operation is also performed on all of said cells sharing a common source line terminal with said selected cell during said performing a write“

0”

operation.

13. The method of claim 8, comprising an individual bit write “

0”

operation, wherein said performing a holding operation comprises performing said holding operation on all of said cells except for said selected cell, while said performing a read or write operation comprises performing a write “

0”

operation on said selected cell.

14. The method of claim 8, wherein said performing a holding operation comprises performing said holding operation on all of said cells except for said selected cell while said performing a read or write operation comprises performing a write “

1”

operation on said selected cell.

15. The method of claim 8, wherein said performing a holding operation comprises performing said holding operation on all of said cells except for said selected cell while said performing a read or write operation comprises performing a multi-level write operation on said selected cell, using an alternating write and verify algorithm.

16. The method of claim 8, wherein said performing a holding operation comprises performing said holding operation on all of said cells except for said selected cell while said performing a read or write operation comprises performing a multi-level write operation on said selected cell, wherein said multi-level write operation includes:

ramping a voltage applied to said selected cell to perform said write operation;

reading the state of said selected cell by monitoring a change in current through said selected cell; and

removing the ramped voltage applied once the change in cell current reaches a predetermined value.

17. The method of claim 8, wherein said performing a holding operation comprises performing said holding operation on all of said cells except for said selected cell while said performing a read or write operation comprises performing a multi-level write operation on said selected cell, wherein said multi-level write operation includes:

ramping a current applied to said selected cell to perform said write operation;

reading the state of said selected cell by monitoring a change in voltage across a bit line and a source line of said selected cell; and

removing the ramped current applied once the change in cell voltage reaches a predetermined value.

18. The method of claim 17, wherein said multi-level write operation permits bit-level selection of a bit portion of memory of said selected cell.

19. The method of claim 8, wherein said performing a holding operation comprises performing said holding operation on all of said cells except for said selected cell while said performing a read or write operation comprises performing a single-level or multi-level write operation on said selected cell, wherein said single-level and each level of said multi-level write operation includes:

ramping a voltage applied to said selected cell to perform said write operation;

reading the state of said selected cell by monitoring a change in current toward an addressable terminal of said selected cell; and

verifying a state of said write operation using a reference memory cell.

20. The method of claim 19, further comprising configuring a state of said reference memory cell using a write-then-verify operation, prior to performing said write operation.

21. The method of claim 19, wherein said configuring a state of said reference memory cell comprises configuring said state upon power up of said memory array.

22. A method of operating a memory array having rows and columns of memory cells assembled into an array of said memory cells, each said memory cell having a floating body region for storing data;

the method comprising;

refreshing a state of at least one of said memory cells comprising inputting to at least one back bias terminal of said at least one of said memory cells; and

accessing at least one other of said memory cells, wherein access of said at least one other of said memory cells is not interrupted by said refreshing, and wherein said refreshing is performed without alternating read and write operations.

23. The method of claim 22, wherein said at least one of said memory cells is a multi-level memory cell.

24. A method of operating a memory array having rows and columns of memory cells assembled into an array of said memory cells, each said memory cell having a floating body region for storing data;

the method comprising;

accessing a selected memory cell from said memory cells;

maintaining unselected memory cells in a holding mode; and

performing a simultaneous write and verify operation on said selected memory cell having been accessed, without performing an alternating write and read operation.

25. The method of claim 24, wherein said selected memory cell having been accessed is a multi-level memory cell.

26. The method of claim 24, wherein a verification portion of said write and verify operation is performed by sensing a current change in the column direction of the array in a column that said selected cell having been accessed is connected to.

27. The method of claim 24, wherein a verification portion of said write and verify operation is performed by sensing a current change in the row direction of the array in a row that said selected cell having been accessed is connected to.

28. The method of claim 24, wherein a write portion of said write and verify operation employs use of a drain or gate voltage ramp.

29. The method of claim 24, wherein a write portion of said write and verify operation employs use of a drain current ramp.