Semiconductor memory device

• US 8,208,328 B2
• Filed: 06/15/2010
• Issued: 06/26/2012
• Est. Priority Date: 06/15/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Hong, Sang Pyo
• Primary Examiner(s): DINH, SON T
• Application Number:
  US12/815,621
• Publication Number:
  US 20100315893A1
• Time in Patent Office: 742 Days
• Field of Search: 365/203, 365/189.11, 365/206, 365/207
• US Class Current: 365/203
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1069 I/O lines read out arrangements
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A semiconductor memory device including a CMOS-type local sensing amplifier circuit is provided. The semiconductor memory device includes a first input/output (I/O) line pair, a second I/O line pair pre-charged to a one-half power voltage level and receives data from the first I/O line pair, and a pull-up circuit pulling up a voltage of one of the second I/O pair to a full power voltage level.

Claims

1. A semiconductor memory device comprising:

a first input/output (I/O) line pair;

a second I/O line pair pre-charged to a one-half power voltage level and configured to receive data from the first I/O line pair; and

a pull-up circuit configured to pull-up a voltage apparent on one of the second I/O line pair to a full power voltage level in response to a control signal.

2. The semiconductor memory device of claim 1, wherein the first I/O line pair is a local data I/O line pair and the second I/O line pair is a global data I/O line pair.

3. The semiconductor memory device of claim 2, wherein the pull-up circuit comprises:

a plurality of P-type MOS transistors controlled in response to the control signal, wherein each one of the plurality of P-type MOS transistors is connected to one of the global data I/O line pair.

4. The semiconductor memory device of claim 3, wherein each one of the plurality of P-type MOS transistors is connected to one of a plurality of N-type MOS transistors configured to control connection to one of the local data I/O line pair in response to a read signal.

5. The semiconductor memory device of claim 4, wherein the read signal and the control signal are complementary signals.

6. The semiconductor memory device of claim 1, wherein the semiconductor memory device further comprises a local sensing amplification circuit and the pull-up circuit is disposed within the local sensing amplification circuit.

7. The semiconductor memory device of claim 1, wherein the semiconductor memory device further comprises a local sensing amplification circuit and the pull-up circuit is disposed outside the local sensing amplification circuit.

8. The semiconductor memory device of claim 1, further comprising:

a bit line sensing amplifier circuit configured to sense/amplify data apparent on a bit line pair and communicate the data to the first I/O line pair;

a local sensing amplifier circuit pre-charged to the one-half power voltage level and configured to sense/amplify data apparent on the first I/O line pair and communicate the data to the second I/O line pair; and

an I/O sensing amplifier circuit pre-charged to the one-half power voltage level and configured to sense/amplifies data apparent on the second I/O line pair,

wherein at least one of the bit line sensing amplifier circuit, the local sensing amplifier circuit, and the I/O sensing amplifier circuit is latch type.

9. The semiconductor memory device of claim 8, wherein the semiconductor memory device further comprises:

a local I/O equalizer circuit configured to equalize the local sensing amplifier circuit, wherein the local I/O equalizer circuit is pre-charged to a full power voltage level.

10. The semiconductor memory device of claim 8, wherein the semiconductor memory device further comprises:

a local I/O equalizer circuit configured to equalize the local sensing amplifier circuit, wherein the local I/O equalizer circuit is pre-charged to the one-half power voltage level.

11. A semiconductor memory device comprising:

a local line and a complementary local line;

a global line connected to the local line and a complementary global line connected to the complementary local line;

a first pre-charge circuit configured to pre-charge the local line and the complementary local line to a one-half power voltage level during a pre-charge operation;

a second pre-charge circuit configured to pre-charge the global line and the complementary global line to the one-half power voltage level during the pre-charge operation; and

a pull-up circuit configured to pull-up a voltage apparent on one of the local line and the complementary local line to a full power voltage level in response to a control signal.

12. The semiconductor memory device of claim 11, wherein the pull-up circuit comprises:

a plurality of P-type MOS transistors controlled in response to the control signal, wherein each one of the plurality of P-type MOS transistors is connected to one of the global data I/O line pair.

13. The semiconductor memory device of claim 12, wherein each one of the plurality of P-type MOS transistors is connected to one of a plurality of N-type MOS transistors configured to control connection to one of the local data I/O line pair in response to a read signal.

14. The semiconductor memory device of claim 13, wherein the read signal and the control signal are complementary signals.

15. The semiconductor memory device of claim 11, wherein the semiconductor memory device further comprises a local sensing amplification circuit and the pull-up circuit is disposed within the local sensing amplification circuit.

16. The semiconductor memory device of claim 11, wherein the semiconductor memory device further comprises a local sensing amplification circuit and the pull-up circuit is disposed outside the local sensing amplification circuit.

17. A method of operating a semiconductor memory device, comprising:

respectively connecting bit lines of a bit line pair with local lines of a local line pair;

precharging the local line pair to a one-half power voltage level;

after pre-charge of the local line pair, communicating data from the bit line pair to the local line pair;

using a local sensing amplifier, sensing/amplifying the data on the local line pair;

precharging a global line pair connected to the local line pair to the one-half power voltage level;

respectively connecting global lines of the global line pair with local lines of the local line pair and communicating the data to the global line pair; and

thereafter,

pulling-down a voltage apparent on one global line of the global line pair while pulling-up a voltage apparent on the other global line of the global line pair, and using a global sensing amplifier, sense/amplifying the data on the global line pair.

18. The method of claim 17, wherein the voltage apparent on the one global line of the global line pair is pulled down to ground and the voltage apparent on the other global line of the global line pair is pulled up to a full power voltage level.

19. The method of claim 18, further comprising:

after sense/amplifying the data on the global line pair, precharging the global line pair to the one-half power voltage level; and

thereafter,

outputting the data.

20. The method of claim 17, wherein the power voltage is VDD.