Digital adaptation circuitry and methods for programmable logic devices

• US 8,208,523 B2
• Filed: 04/04/2011
• Issued: 06/26/2012
• Est. Priority Date: 09/14/2006
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Wong, Wilson, Po Ching Chan, Doris, Shumarayev, Sergey, Maangat, Simardeep, Tri Hoang, Tim, Lai, Tin H., Tran, Thungoc M.
• Primary Examiner(s): Joseph, Jaison
• Application Number:
  US13/079,420
• Publication Number:
  US 20110188564A1
• Time in Patent Office: 449 Days
• Field of Search: 375/229, 375/230, 375/231, 375/232
• US Class Current: 375/229
• CPC Class Codes: H04L 25/03885 adaptive

Abstract

Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.

Claims

1. A method of equalizing a signal, the method comprising:

receiving the signal, the signal comprising a plurality of transition points;

selecting a pattern of bits based, at least in part, on a convergence time of the signal;

detecting an occurrence of the pattern of bits in the signal and identifying a transition point in the signal as the first transition point following the detected occurrence of the pattern of bits;

measuring a set of signal values associated with the first transition point; and

adjusting an equalization level applied to the signal based on the measured set of signal values.

2. The method of claim 1, wherein the set of signal values comprises:

a pre-transition sample value, a transition sample value, and a post-transition sample value.

3. The method of claim 1, further comprising classifying the signal as either over equalized or under equalized based on the measured set of signal values.

4. The method of claim 1, wherein adjusting the equalization level comprises incrementing a boost value by a constant and predetermined amount.

5. The method of claim 1, further comprising extracting a timing signal from the signal.

6. The method of claim 5, further comprising determining a time location for each signal value in the set of signal values based on the timing signal.

7. The method of claim 5, wherein the equalization level is adjusted at a rate slower than an update rate of a clock and data recovery loop.

8. A system comprising:

synchronization circuitry configured to;

receive a signal, the signal comprising a plurality of transition points

select a pattern of bits based, at least in part, on a convergence time of the signal;

detect an occurrence of the pattern of bits in the signal and identify a transition point in the signal as the first transition point following the detected occurrence of the pattern of bits; and

measure a set of signal values associated with the first transition point; and

equalization circuitry configured to adjust an equalization level applied to the signal based on the measured set of signal values.

9. The system of claim 8, wherein the set of signal values comprises:

a pre-transition sample value, a transition sample value, and a post-transition sample value.

10. The system of claim 8, wherein the equalization circuitry is further configured to classify the signal as either over equalized or under equalized based on the measured set of signal values.

11. The system of claim 8, wherein the equalization circuitry is further configured to adjust the equalization level by decrementing a boost value by a constant and predetermined amount.

12. The system of claim 8, wherein the synchronization circuitry is further configured to extract a timing signal from the signal.

13. The system of claim 12, wherein the synchronization circuitry is further configured to determine a time location for each signal value in the set of signal values based on the timing signal.

14. The system of claim 12, wherein the synchronization circuitry is further configured to adjust the equalization level at a rate slower than an update rate of a clock and data recovery loop.

15. A method of equalizing a data signal, the method comprising:

receiving the data signal, the data signal representing a plurality of bits;

determining a reference pattern of bits based, at least in part, on a convergence time of the data signal;

identifying a portion of the data signal as corresponding to bits that match the reference pattern;

identifying a transition point in the data signal as the first transition point following the identified portion of the data signal;

measuring a set of amplitude values associated with the first transition point; and

equalizing the data signal based on the measured set of amplitude values.

16. The method of claim 15, wherein equalizing the data signal comprises counting a number of over equalized samples and a number of under equalized samples from the data signal.

17. The method of claim 15, further comprising extracting a timing signal from the data signal.

18. The method of claim 17, further comprising determining time locations of a set of signal values based on the timing signal.

19. The method of claim 17, wherein the equalizing is performed at a rate that is determined in response to an update rate of a clock and data recovery loop.