Cross-architecture optimization

• US 8,209,524 B2
• Filed: 01/31/2006
• Issued: 06/26/2012
• Est. Priority Date: 08/29/2005
• Status: Expired due to Fees

• Current Assignee: The Invention Science Fund I, L.L.C. (Intellectual Ventures LLC)
• Original Assignee: The Invention Science Fund I, L.L.C. (Intellectual Ventures LLC)
• Inventors: Ferren, Bran, Hillis, W. Daniel, Mangione-Smith, William Henry, Myhrvold, Nathan P., Tegreene, Clarence T., Wood, Lowell L. Jr.
• Primary Examiner(s): Faherty, Corey S
• Application Number:
  US11/343,745
• Publication Number:
  US 20070074173A1
• Time in Patent Office: 2,338 Days
• Field of Search: 712/226
• US Class Current: 712/226
• CPC Class Codes: G06F 8/443 Optimisation
• CPC Class Codes: G06F 8/4441 Reducing the execution time required by the program code

Abstract

Embodiments include a device, apparatus, and a method. An apparatus includes a monitor circuit for determining an execution characteristic of a first instruction associated with a first computing machine architecture. The apparatus also includes a generator circuit for creating an optimization profile useable in an execution of a second instruction associated with a second computing machine architecture.

Claims

1. An apparatus comprising:

a first computing device having a first computing machine architecture;

a second computing device having a second computing machine architecture;

a hardware monitor circuit for determining an execution characteristic of a first instruction associated with the first computing machine architecture; and

a hardware generator circuit for creating a locally generated optimization profile useable in an execution of a second instruction associated with the second computing machine architecture corresponding to the determined execution characteristic of the first instruction associated with the first computing machine architecture, wherein the second computing device includes the hardware generator circuit, and wherein the second instruction associated with the second computing machine architecture is at least substantially different than the first instruction associated with the first computing machine architecture.

2. The apparatus of claim 1, wherein the monitor circuit for determining an execution characteristic of a first instruction associated with a first computing machine architecture includes

circuitry for determining at a runtime an execution characteristic of a first instruction associated with a first computing machine architecture.

3. The apparatus of claim 1, wherein the monitor circuit for determining an execution characteristic of a first instruction associated with a first computing machine architecture includes

circuitry for determining at a walk-time an execution characteristic of a first instruction associated with a first computing machine architecture.

4. The apparatus of claim 1, wherein the monitor circuit for determining an execution characteristic of a first instruction associated with a first computing machine architecture includes

circuitry for determining at a compile time an execution characteristic of a first instruction associated with a first computing machine architecture.

5. The apparatus of claim 1, wherein the monitor circuit for determining an execution characteristic of a first instruction associated with a first computing machine architecture includes

circuitry for dynamically determining an execution characteristic of a first instruction associated with a first computing machine architecture.

6. The apparatus of claim 1, wherein the monitor circuit for determining an execution characteristic of a first instruction associated with a first computing machine architecture includes

circuitry for determining an execution characteristic of a first instruction associated with a first computing machine architecture in response to a compilation of the first instruction into an intermediate language.

7. The apparatus of claim 1, wherein the monitor circuit for determining an execution characteristic of a first instruction associated with a first computing machine architecture includes

circuitry for determining an execution characteristic of a first instruction corresponding to an execution of the first instruction by a real first computing machine having the first computing machine architecture.

8. The apparatus of claim 1, wherein the monitor circuit for determining an execution characteristic of a first instruction associated with a first computing machine architecture includes

circuitry for determining an execution characteristic of a first instruction corresponding to an execution of the first instruction by a virtual first computing machine having the first computing machine architecture.

9. The apparatus of claim 1, wherein the monitor circuit for determining an execution characteristic of a first instruction associated with a first computing machine architecture includes

circuitry for determining an execution characteristic of a first instruction corresponding to a simulated execution of the first instruction having a first computing machine architecture.

10. The apparatus of claim 1, wherein the monitor circuit for determining an execution characteristic of a first instruction associated with a first computing machine architecture includes

circuitry for determining an execution characteristic of a first instruction corresponding to a translation of the first instruction having a first computing machine architecture.

11. The apparatus of claim 1, wherein the monitor circuit for determining an execution characteristic of a first instruction associated with a first computing machine architecture includes

circuitry for determining an execution characteristic of a first instruction corresponding to a dynamic translation of the first instruction associated with a first computing machine architecture.

12. The apparatus of claim 1, wherein the monitor circuit for determining an execution characteristic of a first instruction associated with a first computing machine architecture includes

circuitry for determining an execution characteristic of a first instruction corresponding to a compilation of the first instruction associated with a first computing machine architecture.

13. The apparatus of claim 1, wherein the generator circuit for creating an optimization profile useable in an execution of a second instruction associated with a second computing machine architecture includes

circuitry for creating an optimization profile useable in an execution of a second instruction associated with a second computing machine architecture in response to the determined execution characteristic.

14. The apparatus of claim 1, wherein the second instruction associated with a second computing machine architecture performs at least a substantially similar function as that of the first instruction associated with a first computing machine architecture.

15. The apparatus of claim 1, wherein the generator circuit for creating an optimization profile useable in an execution of a second instruction associated with a second computing machine architecture includes

circuitry for creating an optimization profile useable in modifying a movement of data with respect to an execution of a second instruction associated with a second computing machine architecture.

16. The apparatus of claim 1, wherein the generator circuit for creating an optimization profile useable in an execution of a second instruction associated with a second computing machine architecture includes

circuitry for creating an optimization profile useable in modifying an execution of a second instruction associated with a second computing machine architecture.

25. The apparatus of claim 1, wherein the first computing machine architecture comprises a first instruction set architecture, and wherein the second computing machine architecture comprises a second instruction set architecture.

26. The apparatus of claim 1, wherein the optimization profile useable in the execution of the second instruction associated with the second computing machine architecture comprises optimization information useful when the second instruction is compiled by a virtual machine into a native language of a second computing machine having the second computing machine architecture corresponding to the determined execution characteristic of the first instruction associated with the first computing machine architecture.

30. The apparatus of claim 1, wherein the hardware monitor circuit for determining an execution characteristic of a first instruction associated with a first computing machine architecture includes:

a hardware monitor circuit for determining an execution characteristic of a first instruction associated with a first computing machine architecture wherein the first instruction has a plurality of possible branch outcomes.

31. The apparatus of claim 1, wherein the hardware generator circuit for creating an optimization profile useable in an execution of a second instruction associated with a second computing machine architecture corresponding to the determined execution characteristic of the first instruction associated with the first computing machine architecture includes:

a hardware generator circuit for creating an optimization profile useable in an execution of a second instruction associated with a second computing machine architecture, wherein at least one of the optimization profile or the second instruction has a plurality of possible branch outcomes.

32. The apparatus of claim 1, wherein the locally generated optimization profile points to a non-contiguous third instruction, an instruction associated with the first computing machine architecture, to be fetched in lieu of the first instruction associated with the first computing machine architecture for execution by the first computing machine when indicated by the locally generated optimization profile.

33. The apparatus of claim 1, wherein the hardware generator circuit saves the locally generated optimization profile in an associative cache with the first instruction associated with the first computing machine architecture.

34. The apparatus of claim 1, wherein the locally generated optimization profile is useable in prefetching data in conjunction with an execution of the second instruction associated with the second computing machine architecture in response to receiving data.

17. A method comprising:

identifying an execution characteristic of a first instruction associated with a first computing machine architecture of a first computing device; and

generating locally, in response to the execution characteristic of the first instruction associated with the first computing machine architecture of the first computing device, an optimization profile useable in an execution of a second instruction associated with a second computing machine architecture of a second computing device, wherein the first computing device and the second computing device are included in a same apparatus, and wherein the second instruction associated with the second computing machine architecture is at least substantially different than the first instruction associated with the first computing machine architecture.

18. The method of claim 17, wherein the identifying an execution characteristic of a first instruction associated with a first computing machine architecture of a first computing device includes

identifying an execution characteristic of a first instruction associated with a first computing machine architecture of a first computing device in an environment that includes at least one of a dynamic execution environment, a runtime execution environment, a walk-time execution environment, and/or a static environment.

19. The method of claim 17, wherein the generating an optimization profile useable in an execution of a second instruction associated with a second computing machine architecture includes

generating an optimization profile useable in an execution of a second instruction associated with a second computing machine architecture corresponding to the identified execution characteristic.

27. The method of claim 17 wherein the first computing machine architecture comprises a first set of machine language instructions, and wherein the second computing machine architecture comprises a second set of machine language instructions.

20. A device comprising:

a hardware means for determining an execution characteristic of a first instruction associated with a first computing machine architecture of a first computing machine; and

means for creating locally an optimization profile useable in an execution of a second instruction associated with a second computing machine architecture of a second computing machine corresponding to the determined execution characteristic of the first instruction associated with the first computing machine architecture of the first computing device, wherein the first computing machine and the second computing machine are included in the device, and wherein the second instruction associated with the second computing machine architecture of the second computing machine is at least substantially different than the first instruction associated with the first computing machine architecture.

28. The device of claim 20 wherein the first computing machine architecture comprises a first set of machine language instructions, and wherein the second computing machine architecture comprises a second set of machine language instructions.

21. An apparatus comprising:

an optimization profile usable during an execution of a second instruction associated with a second computing machine architecture of a second computing machine and determined locally in response to an execution characteristic of a first instruction associated with a first computing machine architecture of a first computing machine, wherein the first computing machine and the second computing machine are included in the apparatus, and wherein the second instruction associated with the second computing machine architecture of the second computing machine is at least substantially different than the first instruction associated with the first computing machine architecture; and

a computer-readable storage medium encoded with the optimization profile.

22. The apparatus of claim 21, wherein the computer-readable storage medium includes a computer storage medium.

23. The apparatus of claim 22, wherein the computer storage medium includes a transportable computer storage medium.

24. The apparatus of claim 22, wherein the computer storage medium includes a portable computer storage medium.

29. The apparatus of claim 21 wherein the first computing machine architecture comprises a first set of machine language instructions, and wherein the second computing machine architecture comprises a second set of machine language instructions.