Efficient interference cancellation in analog memory cell arrays

• US 8,209,588 B2
• Filed: 12/11/2008
• Issued: 06/26/2012
• Est. Priority Date: 12/12/2007
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Anobit Technologies, Ltd. (Apple Inc.)
• Inventors: Perlmutter, Uri, Kasorla, Yoav, Golov, Oren
• Primary Examiner(s): Riad, Amine
• Application Number:
  US12/332,368
• Publication Number:
  US 20090158126A1
• Time in Patent Office: 1,293 Days
• Field of Search: 714/773
• US Class Current: 714/773
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 2029/5002 Characteristic
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing

Abstract

A method includes storing data in a group of analog memory cells by writing first storage values to the cells. After storing the data, second storage values are read from the cells using one or more first read thresholds. Third storage values that potentially cause cross-coupling interference in the second storage values are identified, and the third storage values are processed, to identify a subset of the second storage values as severely-interfered values. Fourth storage values are selectively re-read from the cells holding the severely-interfered values using one or more second read thresholds, different from the first read thresholds. The cross-coupling interference in the severely-interfered storage values is canceled using the re-read fourth storage values. The second storage values, including the severely-interfered values in which the cross-coupling interference has been canceled, are processed so as to reconstruct the data stored in the cell group.

Claims

1. A method for operating a memory that includes analog memory cells, the method comprising:

storing data in a group of the analog memory cells by writing respective first storage values to the memory cells in the group;

after storing the data, reading respective second storage values from the memory cells in the group using one or more first read thresholds;

identifying third storage values that potentially cause cross-coupling interference in the second storage values, and processing the third storage values so as to identify a subset of the second storage values as severely-interfered storage values;

selectively re-reading respective fourth storage values from the memory cells holding the severely-interfered storage values using one or more second read thresholds, different from the first read thresholds;

canceling the cross-coupling interference in the severely-interfered storage values using the re-read fourth storage values; and

processing the second storage values, including the severely-interfered storage values in which the cross-coupling interference has been canceled, so as to reconstruct the data stored in the group of the memory cells.

2. The method according to claim 1, wherein storing the data comprises encoding the data with an Error Correction Code (ECC), wherein reading the second storage values comprises decoding the ECC, and comprising re-reading the fourth storage values and canceling the cross-coupling interference responsively to a failure in decoding the ECC.

3. The method according to claim 1, wherein processing the third storage values comprises calculating respective expected levels of the cross-coupling interference in the second storage values caused by the third storage values, and selecting the severely-interfered storage values responsively to the expected levels.

4. The method according to claim 1, wherein storing the data comprises programming the memory cells to assume multiple programming levels, wherein reading the second storage values comprises comparing the second storage values to a given read threshold that differentiates between first and second adjacent programming levels, and wherein processing the third storage values comprises selecting the severely-interfered storage values only from among the second storage values corresponding to the first and second programming levels.

5. The method according to claim 1, wherein processing the third storage values comprises determining a classification of the second storage values into a first subset of the second storage values that are increased due to the cross-coupling interference, and a second subset of the second storage values that are decreased due to the cross-coupling interference, and identifying the severely-interfered storage values responsively to the classification.

6. The method according to claim 1, wherein selectively re-reading the fourth storage values comprises refraining from re-reading the fourth storage values from at least some of the memory cells that do not hold the severely-interfered storage values.

7. The method according to claim 1, wherein selectively re-reading the fourth storage values comprises transferring the fourth storage values from the memory cells over an interface to a controller, and wherein canceling the cross-coupling interference comprises canceling the cross-coupling interference in the controller.

8. The method according to claim 7, wherein transferring the fourth storage values comprises transferring over the interface only the fourth storage values that were re-read from the memory cells holding the severely-interfered storage values.

9. The method according to claim 8, wherein selectively re-reading the fourth storage values comprises sensing the fourth storage values of all the memory cells in the group.

10. The method according to claim 8, wherein selectively re-reading the fourth storage values comprises refraining from sensing the fourth storage values of the memory cells that do not hold the severely-interfered storage values.

11. The method according to claim 7, wherein selectively re-reading the fourth storage values comprises sending from the controller over the interface an instruction to enter a predefined reading mode, the instruction indicating the group of the memory cells from which the fourth storage values are to be re-read when operating in the predefined mode.

12. The method according to claim 11, wherein, when operating in the predefined reading mode, selectively re-reading the fourth storage values comprises sending from the controller read requests specifying respective addresses of the fourth storage values within the group, and re-reading the fourth storage values responsively to the read requests.

13. The method according to claim 12, wherein sending the read requests comprises specifying a given address of a given fourth storage value requested in a given read request by specifying in the given read request an offset of the given address from a previous address of a previous fourth storage value requested in a previous read request that precedes the given read request.

14. The method according to claim 7, wherein identifying and processing the third storage values comprise sending from the controller over the interface a criterion for identifying the severely-interfered storage values based on the third storage values, and identifying the severely-interfered storage values responsively to the criterion.

15. A data storage apparatus, comprising:

a memory, which comprises a plurality of analog memory cells; and

circuitry, which is coupled to store data in a group of the analog memory cells by writing respective first storage values to the memory cells in the group, to read respective second storage values from the memory cells in the group using one or more first read thresholds after storing the data, to identify third storage values that potentially cause cross-coupling interference in the second storage values, to process the third storage values so as to identify a subset of the second storage values as severely-interfered storage values, to electively re-read respective fourth storage values from the memory cells holding the severely-interfered storage values using one or more second read thresholds, different from the first read thresholds, to cancel the cross-coupling interference in the severely-interfered storage values using the re-read fourth storage values, and to process the second storage values, including the severely-interfered storage values in which the cross-coupling interference has been canceled, so as to reconstruct the data stored in the group of the memory cells.

16. The apparatus according to claim 15, wherein the circuitry is coupled to encode the stored data with an Error Correction Code (ECC), to decode the ECC responsively to the read second storage values, and to re-read the fourth storage values and cancel the cross-coupling interference responsively to a failure in decoding the ECC.

17. The apparatus according to claim 15, wherein the circuitry is coupled to calculate respective expected levels of the cross-coupling interference in the second storage values caused by the third storage values, and to select the severely-interfered storage values responsively to the expected levels.

18. The apparatus according to claim 15, wherein the circuitry is coupled to program the memory cells to assume multiple programming levels, to read the second storage values by comparing the second storage values to a given read threshold that differentiates between first and second adjacent programming levels, and to select the severely-interfered storage values only from among the second storage values corresponding to the first and second programming levels.

19. The apparatus according to claim 15, wherein the circuitry is coupled to determine a classification of the second storage values into a first subset of the second storage values that are increased due to the cross-coupling interference, and a second subset of the second storage values that are decreased due to the cross-coupling interference, and to identify the severely-interfered storage values responsively to the classification.

20. The apparatus according to claim 15, wherein the circuitry is coupled to refrain from re-reading the fourth storage values from at least some of the memory cells that do not hold the severely-interfered storage values.

21. The apparatus according to claim 15, wherein the circuitry comprises:

a Read/Write (R/W) unit, which is packaged in a memory device comprising the memory cells and which is coupled to selectively re-read the fourth storage values and to export the fourth storage values from the memory device over an interface; and

a memory controller, which is external to the memory device and is coupled to receive the fourth storage values over the interface and to cancel the cross-coupling interference using the received fourth storage values.

22. The apparatus according to claim 21, wherein the R/W unit is coupled to transfer over the interface only the fourth storage values that were re-read from the memory cells holding the severely-interfered storage values.

23. The apparatus according to claim 22, wherein the R/W unit is coupled to selectively re-read the fourth storage values by sensing the fourth storage values of all the memory cells in the group.

24. The apparatus according to claim 22, wherein the R/W unit is coupled to selectively re-read the fourth storage values by refraining from sensing the fourth storage values of the memory cells that do not hold the severely-interfered storage values.

25. The apparatus according to claim 21, wherein the memory controller is coupled to send to the R/W unit an instruction to enter a predefined reading mode, the instruction indicating the group of the memory cells from which the fourth storage values are to be re-read when operating in the predefined mode.

26. The apparatus according to claim 25, wherein, when operating in the predefined reading mode, the memory controller is coupled to send to the R/W unit read requests specifying respective addresses of the fourth storage values within the group, and wherein the R/W unit is coupled to re-read the fourth storage values responsively to the read requests.

27. The apparatus according to claim 26, wherein the memory controller is coupled to specify a given address of a given fourth storage value requested in a given read request by specifying in the given read request an offset of the given address from a previous address of a previous fourth storage value requested in a previous read request that precedes the given read request.

28. The apparatus according to claim 21, wherein the memory controller is coupled to send to the R/W unit a criterion for identifying the severely-interfered storage values based on the third storage values, and wherein the R/W unit is coupled to identify the severely-interfered storage values responsively to the criterion.