Verifying multiple constraints for circuit designs

• US 8,209,648 B1
• Filed: 09/03/2009
• Issued: 06/26/2012
• Est. Priority Date: 09/03/2009
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Ku, Shan-Chyun, Glusman, Marcelo, Hsieh, Yee-Wing, Pandey, Manish, Krstic, Angela, Kirihennedige, Sarath
• Primary Examiner(s): Doan, Nghia
• Application Number:
  US12/553,965
• Time in Patent Office: 1,027 Days
• Field of Search: 716/108, 716/111, 716113-114, 716/122, 716/134, 716/136
• US Class Current: 716/108
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

Certain embodiments of the present invention enable comparisons between constrained circuit designs by generating timing graphs for circuit designs, mapping timing constraints to the timing graphs, and comparing the mapped timing constraints from different timing graphs. Typically this comparison is made by identifying corresponding nodes in two or more timing graphs. Specific embodiments are also directed to multiple SDC (Synopsis Design Constraint) constraint specifications for a circuit and multiple constraint sets for different operational modes of a circuit.

Claims

1. A method of evaluating constrained circuit designs, comprising:

specifying a plurality of constrained designs, wherein each constrained design includes a circuit design that includes circuit elements and connections between circuit elements, and each constrained design further includes timing constraints for paths along the connections between circuit elements, the timing constraints including one or more timing exceptions including false paths that are not active paths, multi-cycle paths that correspond to multiple clock cycles, maximum delays along paths, or minimum delays along paths;

generating a timing graph for each circuit design, wherein each timing graph includes nodes corresponding to circuit elements and edges corresponding to connections between circuit elements;

mapping the timing constraints for each circuit design to a timing-graph constraint set for a corresponding timing graph;

using a computer to evaluate the constrained designs by comparing the timing-graph constraint sets and determining a presence or absence of one or more paths with a constraint error that corresponds to an inconsistent, conflicting or missing constraint; and

providing a timing-constraint report to a user, wherein the timing-constraint report includes values for the presence or absence of one or more paths with a constraint error.

2. A method according to claim 1, wherein evaluating the constrained designs includes identifying nodes of each timing graph with corresponding nodes of other graphs so that elements of timing constraint sets are correspondingly identified.

3. A method according to claim 1, wherein the timing-constraint report shows the presence of one or more paths with a constraint error including a first path in a first circuit design, wherein the first path is an unconstrained active path.

4. A method according to claim 1, wherein the timing-constraint report shows the presence of one or more paths with a constraint error including a first path in a first circuit design or a second path in a second circuit design, wherein

the first path is equivalent to the second path, and

a first-path constraint for a minimum or maximum delay is inconsistent with a second-path constraint for a minimum or maximum delay.

5. A method according to claim 1, wherein the timing-constraint report shows the presence of one or more paths with a constraint error including a first path in a first circuit design or a second path in a second circuit design, wherein

the first path is equivalent to the second path, and

a first-path constraint for a minimum delay conflicts with a second-path constraint for a maximum delay.

6. A method according to claim 1, wherein the timing-constraint report shows the presence of one or more paths with a constraint error including a first path in a first circuit design or a second path in a second circuit design, wherein

the first path is equivalent to the second path, and

the first path is constrained as a multi-cycle path and the second path is not constrained as a multi-cycle path.

7. A method according to claim 1, wherein

the constrained designs correspond to a plurality of modes for operation of a common circuit design, and

the timing-constraint report shows the presence of one or more paths with a constraint error including a first path of the circuit design, wherein the first path is unconstrained across the modes for operation of the common circuit design.

8. A non-transitory computer-readable medium that stores a computer program for evaluating constrained circuit designs, wherein the computer program includes instructions for:

specifying a plurality of constrained designs, wherein each constrained design includes a circuit design that includes circuit elements and connections between circuit elements, and each constrained design further includes timing constraints for paths along the connections between circuit elements, the timing constraints including one or more timing exceptions including false paths that are not active paths, multi-cycle paths that correspond to multiple clock cycles, maximum delays along paths, or minimum delays along paths;

generating a timing graph for each circuit design, wherein each timing graph includes nodes corresponding to circuit elements and edges corresponding to connections between circuit elements;

mapping the timing constraints for each circuit design to a timing-graph constraint set for a corresponding timing graph;

evaluating the constrained designs by comparing the timing-graph constraint sets and determining a presence or absence of one or more paths with a constraint error that corresponds to an inconsistent, conflicting or missing constraint; and

providing a timing-constraint report to a user, wherein the timing-constraint report includes values for the presence or absence of one or more paths with a constraint error.

9. A non-transitory computer-readable medium according to claim 8, wherein evaluating the constrained designs includes identifying nodes of each timing graph with corresponding nodes of other graphs so that elements of timing constraint sets are correspondingly identified.

10. A non-transitory computer-readable medium according to claim 8, wherein the timing-constraint report shows the presence of one or more paths with a constraint error including a first path in a first circuit design, wherein the first path is an unconstrained active path.

11. A non-transitory computer-readable medium according to claim 8, wherein the timing-constraint report shows the presence of one or more paths with a constraint error including a first path in a first circuit design or a second path in a second circuit design, wherein

the first path is equivalent to the second path, and

a first-path constraint for a minimum or maximum delay is inconsistent with a second-path constraint for a minimum or maximum delay.

12. A non-transitory computer-readable medium according to claim 8, wherein the timing-constraint report shows the presence of one or more paths with a constraint error including a first path in a first circuit design or a second path in a second circuit design, wherein

the first path is equivalent to the second path, and

a first-path constraint for a minimum delay conflicts with a second-path constraint for a maximum delay.

13. A non-transitory computer-readable medium according to claim 8, wherein the timing-constraint report shows the presence of one or more paths with a constraint error including a first path in a first circuit design or a second path in a second circuit design, wherein

the first path is equivalent to the second path, and

the first path is constrained as a multi-cycle path and the second path is not constrained as a multi-cycle path.

14. A non-transitory computer-readable medium according to claim 8, wherein

the constrained designs correspond to a plurality of modes for operation of a common circuit design, and

the timing-constraint report shows the presence of one or more paths with a constraint error including a first path of the circuit design, wherein the first path is unconstrained across the modes for operation of the common circuit design.

15. An apparatus for evaluating constrained circuit designs, the apparatus comprising a computer for executing computer instructions, wherein the computer includes computer instructions for:

specifying a plurality of constrained designs, wherein each constrained design includes a circuit design that includes circuit elements and connections between circuit elements, and each constrained design further includes timing constraints for paths along the connections between circuit elements, the timing constraints including one or more timing exceptions including false paths that are not active paths, multi-cycle paths that correspond to multiple clock cycles, maximum delays along paths, or minimum delays along paths;

generating a timing graph for each circuit design, wherein each timing graph includes nodes corresponding to circuit elements and edges corresponding to connections between circuit elements;

mapping the timing constraints for each circuit design to a timing-graph constraint set for a corresponding timing graph;

evaluating the constrained designs by comparing the timing-graph constraint sets and determining a presence or absence of one or more paths with a constraint error that corresponds to an inconsistent, conflicting or missing constraint; and

providing a timing-constraint report to a user, wherein the timing-constraint report includes values for the presence or absence of one or more paths with a constraint error.

16. An apparatus according to claim 15, wherein the computer includes a processor with memory for executing at least some of the computer instructions.

17. An apparatus according to claim 15, wherein the computer includes circuitry for executing at least some of the computer instructions.

18. An apparatus according to claim 15, wherein the timing-constraint report shows the presence of one or more paths with a constraint error including a first path in a first circuit design or a second path in a second circuit design, wherein

the first path is equivalent to the second path, and

a first-path constraint for a minimum or maximum delay is inconsistent with a second-path constraint for a minimum or maximum delay.

19. An apparatus according to claim 15, wherein the timing-constraint report shows the presence of one or more paths with a constraint error including a first path in a first circuit design or a second path in a second circuit design, wherein

the first path is equivalent to the second path, and

a first-path constraint for a minimum delay conflicts with a second-path constraint for a maximum delay.

20. An apparatus according to claim 15, wherein the timing-constraint report shows the presence of one or more paths with a constraint error including a first path in a first circuit design or a second path in a second circuit design, wherein

the first path is equivalent to the second path, and

the first path is constrained as a multi-cycle path and the second path is not constrained as a multi-cycle path.

21. An apparatus according to claim 15, wherein

the constrained designs correspond to a plurality of modes for operation of a common circuit design, and

the timing-constraint report shows the presence of one or more paths with a constraint error including a first path of the circuit design, wherein the first path is unconstrained across the modes for operation of the common circuit design.