Method of making transistor having metal gate

• US 8,211,775 B1
• Filed: 03/09/2011
• Issued: 07/03/2012
• Est. Priority Date: 03/09/2011
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Hung, Wen-Han, Lo, Ta-Kang, Chen, Tsai-Fu, Cheng, Tzyy-Ming, Ma, Cheng-Yu
• Primary Examiner(s): Lee, Cheung
• Application Number:
  US13/043,479
• Time in Patent Office: 482 Days
• Field of Search: 438/183, 438/184, 438/774, 438/926, 257/E21.4, 257/E21.457, 257/E21.536
• US Class Current: 438/287
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

A method for forming a transistor having a metal gate is provided. A substrate is provided first. A transistor is formed on the substrate. The transistor includes a high-k gate dielectric layer, an oxygen containing dielectric layer disposed on the high-k gate dielectric layer, and a dummy gate disposed on the oxygen containing dielectric layer. Then, the dummy gate and the patterned gate dielectric layer are removed. Lastly, a metal gate is formed and the metal gate directly contacts the high-k gate oxide.

Claims

1. A method for forming a transistor having a metal gate, comprising:

providing a substrate;

forming a transistor on the substrate, wherein the transistor comprises a high-k gate dielectric layer, an oxygen containing dielectric layer disposed on and directly contacting the high-k gate dielectric layer and a dummy gate disposed on the oxygen containing dielectric layer;

removing the dummy gate and the oxygen containing dielectric layer on the high-k gate dielectric layer; and

forming a metal gate, wherein the metal gate directly contacts the high-k gate dielectric layer.

2. The method for forming a transistor having a metal gate according to claim 1, wherein the oxygen containing dielectric layer comprises SiO₂, SiOF or SiON.

3. The method for forming a transistor having a metal gate according to claim 1, wherein in the step of forming the transistor, there is no metal layer between the dummy gate and the high-k gate dielectric layer.

4. The method for forming a transistor having a metal gate according to claim 1, wherein the dummy gate is removed first, and then the oxygen containing dielectric layer is removed.

5. The method for forming a transistor having a metal gate according to claim 4, wherein the step of removing the dummy gate comprises a wet etching step.

6. The method for forming a transistor having a metal gate according to claim 4, wherein the step of removing the oxygen containing dielectric layer comprises a dry etching step.

7. The method for forming a transistor having a metal gate according to claim 1, wherein the high-k gate dielectric layer is a metal oxide layer.

8. The method for forming a transistor having a metal gate according to claim 7, wherein the metal comprises rare earth metal.

9. The method for forming a transistor having a metal gate according to claim 7, wherein the high-k gate dielectric layer comprises hafnium oxide (HfO₂), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), aluminum oxide (AlO), lanthanum oxide (La₂O₃), lanthanum aluminum oxide (LaAlO), tantalum oxide, Ta₂O₃, zirconium oxide (ZrO₂), zirconium silicon oxide (ZrSiO), hafnium zirconium oxide (HfZrO), strontium bismuth tantalite (SrBi₂Ta₂O₉, SBT), lead zirconate titanate (PbZr_xTi_1-xO₃, PZT) or barium strontium titanate (Ba_xSr_1-xTiO₃, BST).

10. The method for forming a transistor having a metal gate according to claim 1, wherein the transistor further comprises an interface gate dielectric layer disposed between the substrate and the high-k gate dielectric layer and the interface gate dielectric layer directly contacts the high-k gate dielectric layer.

11. The method for forming a transistor having a metal gate according to claim 10, wherein the interface gate dielectric layer comprises silicon oxide or nitradation silicon oxide.

12. The method for forming a transistor having a metal gate according to claim 10, wherein the step of forming the transistor comprises:

forming an interface layer, a high-k dielectric layer, an oxide layer and a dummy gate layer on the substrate in sequence; and

performing a patterning process to form the interface gate dielectric layer, the high-k gate dielectric layer, the oxygen containing dielectric layer and the dummy gate.

13. The method for forming a transistor having a metal gate according to claim 12, wherein the step of forming the transistor further comprises:

forming a spacer on a sidewall of the interface gate dielectric layer, the high-k gate dielectric layer, the oxygen containing dielectric layer and the dummy gate;

performing an implant process by using the spacer as a mask to form a source/drain in the substrate; and

performing a source/drain annealing process.

14. The method for forming a transistor having a metal gate according to claim 13, wherein the source/drain annealing process is performed above 1000 degrees.