Method for fabricating circuitry component

• US 8,211,791 B2
• Filed: 03/05/2003
• Issued: 07/03/2012
• Est. Priority Date: 12/13/2001
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan, Huang, Ching-Cheng
• Primary Examiner(s): ZARNEKE, DAVID A
• Application Number:
  US10/382,699
• Publication Number:
  US 20030148604A1
• Time in Patent Office: 3,408 Days
• Field of Search: 438/622, 438625-629, 438/633, 438/624, 438/666
• US Class Current: 438/624
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.

Claims

1. A method for fabricating a chip, comprising:

providing a wafer with a silicon substrate, a transistor on said silicon substrate, a first metal layer over said silicon substrate, a second metal layer over said silicon substrate and said first metal layer, a dielectric layer between said first and second metal layers, and a separating layer over said silicon substrate, said first and second metal layers and said dielectric layer, wherein a first opening in said separating layer is over a contact point of said second metal layer, and said contact point is at a bottom of said first opening;

forming a first polymer layer on said separating layer, wherein a second opening passes vertically through said first polymer layer and is vertically over said contact point, said first opening and a first region of a top surface of said separating layer;

forming a second polymer layer on said first polymer layer, wherein a third opening passes vertically through said second polymer layer and is vertically over said contact point, said first and second openings, said first region and a second region of a top surface of said first polymer layer;

forming a third metal layer in said first, second and third openings, on a sidewall of said first opening, on a sidewall of said second opening, on a sidewall of said third opening, on a top surface of said second polymer layer, on said first and second regions, and over said separating layer;

forming a fourth metal layer in said second and third openings, and over said top surface of said second polymer layer, said first and second regions, said third metal layer, and said separating layer using a process comprising an electroplating process;

after said forming said fourth metal layer, removing said third and fourth metal layers over said top surface of said second polymer layer using a process comprising a polishing process; and

forming a third polymer layer on said fourth metal layer, on said second polymer layer, and over said separating layer.

2. The method of claim 1, wherein said electroplating process comprises a gold electroplating process.

3. The method of claim 1, wherein said electroplating process comprises a nickel electroplating process.

4. The method of claim 1, wherein said forming said third metal layer comprises a sputtering process.

5. The method of claim 1, wherein said electroplating process comprises a copper electroplating process.

6. The method of claim 1, wherein said polishing process comprises a chemical-mechanical polishing (CMP) process.

7. The method of claim 1, wherein said separating layer comprises an oxide.

8. The method of claim 1, wherein said separating layer comprises silicon nitride.

9. The method of claim 1, wherein said forming said first polymer layer comprises a spin-coating process.

10. The method of claim 1, wherein said forming said second polymer layer comprises a spin-coating process.

11. The method of claim 1, wherein said separating layer comprises a nitride.