Structures electrically connecting aluminum and copper interconnections and methods of forming the same

• US 8,211,793 B2
• Filed: 03/01/2010
• Issued: 07/03/2012
• Est. Priority Date: 08/18/2006
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jong-Myeong, Lee, Sang-Woo, Choi, Gil-Heyun, Hong, Jong-Won, Choi, Kyung-In, Lee, Hyun-Bae
• Primary Examiner(s): Kebede, Brook
• Application Number:
  US12/714,704
• Publication Number:
  US 20100151674A1
• Time in Patent Office: 855 Days
• Field of Search: 438618-639, 257/E21.579
• US Class Current: 438/637
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A structure and formation method for electrically connecting aluminum and copper interconnections stabilize a semiconductor metallization process using an inner shape electrically connecting the aluminum and copper interconnections. To this end, a copper interconnection is disposed on a semiconductor substrate. An interconnection induction layer and an interconnection insertion layer are sequentially formed on the copper interconnection to have a contact hole exposing the copper interconnection. An upper diameter of the contact hole may be formed to be larger than a lower diameter thereof. A barrier layer and an aluminum interconnection are filled in the contact hole. The aluminum interconnection is formed not to directly contact the copper interconnection through the contact hole.

Claims

1. A method of fabricating a structure in a semiconductor device, comprising:

forming a lower metal interconnection;

forming a lower insulating layer defining a lower contact hole on the lower metal interconnection, the lower insulating layer exposing a portion of a surface of the lower metal interconnection;

forming an upper insulating layer defining an upper contact hole wider than the lower contact hole on the lower metal interconnection, the upper insulating layer fully exposing the lower contact hole and a portion of a top surface of the lower insulating layer, the portion of the top surface of the lower insulating layer being around the lower contact hole, wherein a depth of the lower contact hole is shallower than a depth of the upper contact hole;

forming a contact spacer disposed on sidewalls of the lower contact hole and the upper contact hole, wherein the contact spacer exposes a portion of the lower metal interconnection and covers an entire surface of the portion of the top surface of the lower insulating layer exposed by the upper insulating layer to smooth an inner shape formed by a step difference of the lower contact hole and the upper contact hole;

forming a barrier pattern on the exposed surface of the lower metal interconnection, the contact spacer and a portion of a top surface of the upper insulating layer;

forming a lower contact directly on the barrier pattern, wherein the lower contact fills the lower contact hole;

forming an upper contact directly on the barrier pattern, wherein the upper contact fills the upper contact hole; and

forming an upper metal interconnection directly on the upper contact and the barrier pattern on the portion of the top surface of the upper insulating layer.

2. The method according to claim 1, wherein the barrier pattern has a first thickness on the sidewalls of the lower insulating layer and a second thickness on the exposed portion of the surface of the lower metal interconnection, the second thickness being thicker than the first thickness.

3. The method according to claim 1, wherein the barrier pattern has a third thickness on the sidewalls of the upper insulating layer and a fourth thickness on the portion of the top surface of the upper insulating layer, the fourth thickness being thicker than the third thickness.

4. The method according to claim 1, further comprising:

forming a middle insulating layer defining a middle contact hole on the lower insulating layer.

5. The method according to claim 4, wherein the middle insulating layer exposes a portion of a surface of the lower insulating layer and the upper insulating layer exposes a portion of a surface of the middle insulating layer.

6. The method according to claim 4, wherein the lower insulating layer includes a silicon-rich silicon nitride layer and the middle insulating layer includes a nitrogen-rich silicon nitride layer.

7. The method according to claim 4, wherein the middle contact hole is wider than the lower contact hole and narrower than the upper contact hole.

8. The method according to claim 1, wherein the lower insulating layer includes a silicon nitride layer.

9. The method according to claim 1, wherein a maximum thickness of the barrier pattern on the exposed surface of the lower metal interconnection is greater than the depth of the lower contact hole.

10. The method according to claim 9, wherein the barrier pattern fully fills the lower contact hole.

11. A method of fabricating a structure on a semiconductor device, comprising:

forming a lower metal interconnection, forming a lower insulating layer on the lower metal interconnection, forming an upper insulating layer on the lower insulating layer;

forming a photoresist pattern having an opening overlapping the lower metal interconnection;

forming an upper contact hole and a lower contact hole by patterning the upper insulating layer and the lower insulating layer using the photoresist pattern as a patterning mask, wherein the upper contact hole is defined by the upper insulating layer and the lower contact hole is defined by the lower insulating layer;

partially removing a portion of the upper insulating layer in the upper contact hole so that the upper contact hole has a larger width and a deeper depth than that of the lower contact hole;

removing the photoresist pattern;

forming a contact spacer disposed on sidewalls of the lower and upper contact holes and an entire surface of the lower insulating layer exposed by the upper contact hole to smooth an inner shape formed by a step difference of the lower contact hole and the upper contact hole, wherein the contact spacer exposes a portion of the lower metal interconnection;

forming a barrier pattern on the exposed surface of the lower metal interconnection, the contact spacer and a portion of a top surface of the upper insulating layer;

forming a lower contact directly on the barrier pattern, wherein the lower contact fills the lower contact hole;

forming an upper contact directly on the barrier pattern, wherein the upper contact fills the upper contact hole; and

forming an upper metal interconnection directly on the barrier pattern on the portion of the top surface of the upper insulating layer.

12. The method according to claim 11, wherein partially removing the portion of the upper insulating layer in the upper contact hole is performed by isotropic etching.

13. The method according to claim 12, wherein the upper insulating layer has a different etch rate than the lower insulating layer during the isotropic etching.

14. The method according to claim 11, further comprising:

forming a middle insulating layer between the lower insulating layer and the upper insulating layer.

15. The method according to claim 14, further comprising forming a middle contact hole by patterning the middle insulating layer using the photoresist pattern as the patterning mask.

16. The method according to claim 15, wherein the middle contact hole is wider than the lower contact hole and narrower than the upper contact hole.

17. The method according to claim 15, wherein the lower insulating layer includes a silicon-rich silicon nitride layer and the middle insulating layer includes a nitrogen-rich silicon nitride layer.

18. The method according to claim 11, further comprising patterning both of the upper metal interconnection and the barrier pattern to leave both of the upper metal interconnection and the barrier pattern on the top surface on the upper insulating layer.

19. A method of fabricating a structure on a semiconductor device, comprising:

forming a copper interconnection;

forming a lower insulating layer defining a lower contact hole exposing a portion of the copper interconnection, the lower insulating layer exposing a portion of a surface the copper interconnection;

forming an upper insulating layer defining an upper contact hole wider than the lower contact hole on the copper interconnection, the upper insulating layer fully exposing the lower contact hole and a portion of a top surface of the lower insulating layer, the portion of the top surface of the lower insulating layer being around the lower contact hole;

forming a barrier layer on the exposed portion of the copper interconnection, sidewalls of the lower and upper contact holes, and a top surface of the upper insulating layer, wherein the barrier layer has a first thickness on the exposed portion of the copper interconnection and a second thickness on the sidewall of the upper insulating layer, the first thickness being thicker than the second thickness, and wherein the barrier layer fills the lower contact hole;

forming an aluminum layer filing the lower and upper contact holes on the exposed portion of the copper interconnection and the top surface of the upper insulating layer, wherein the aluminum layer has a first portion in the lower and upper contact holes, a second portion on the first portion and the top surface of the upper insulating layer, wherein the aluminum layer is directly formed on a barrier pattern; and

selectively removing and leaving the aluminum layer and the barrier layer on the top surface of the upper insulating layer to form an aluminum interconnection and the barrier pattern, wherein sidewalls of the aluminum interconnection and the barrier pattern are vertically aligned with each other on the top surface of the upper insulating layer.

20. The method according to claim 19, wherein selectively removing and leaving the aluminum layer and the barrier layer comprise a dry etching process.