Integrated passive device

• US 8,212,155 B1
• Filed: 06/26/2007
• Issued: 07/03/2012
• Est. Priority Date: 06/26/2007
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: TriQuint Semiconductor Incorporated (Qorvo, Inc.)
• Inventors: Wright, Peter V., Mays, Kenneth
• Primary Examiner(s): Chen, Xiaoliang
• Application Number:
  US11/823,413
• Time in Patent Office: 1,834 Days
• Field of Search: 174/263, 174/259, 174/260, 361/760, 361/311, 336/200, 257/300, 257/778
• US Class Current: 174/263
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01L 23/00 Details of semiconductor or other solid state devices H01L25/00 takes precedence ; structural arrangements for testing or measuring during manufacture or treatment, or for reliability measurements H01L22/00; arrangements for connecting or disconnecting semiconductor or solid-state bodies, or methods related thereto H01L24/00; finger print sensors G06V40/12
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Embodiments of an integrated passive device include a high-aspect ratio conductive line positioned on a carrier, a substrate, and a bump that secures the high-aspect ratio conductive line to the substrate.

Claims

1. An integrated passive device, comprising:

a first conductive line section positioned on a planar topmost surface of a carrier and having width W and thickness T, where T/W at least 0.5;

a second conductive line section positioned on said planar topmost surface of said carrier wherein a nearest distance from said second conductive line section to said first conductive line section is S, where S is at most 1.5.T;

a substrate; and

a bump positioned directly on said first conductive line section, said bump including a height that has a region of a high melting-point conductor and a region of a low melting-point conductor, said bump securing said first conductive line section to said substrate and having a height of at least 30 μ

m wherein said bump is positioned between said first conductive line section and said substrate.

2. The device of claim 1 wherein said first conductive line section is a portion of a first integrated passive component, and wherein said second conductive line section is chosen from one of another section of said first integrated passive component and a section of a second integrated passive component.

3. The device of claim 1 wherein the bump is mounted directly to an upper surface of the first conductive line section.

4. The device of claim 1 wherein the region of the high melting-point conductor of said bump is positioned directly on said first conductive line section prior to securement of said first conductive line section to said substrate.

5. The device of claim 1 wherein the high melting-point conductor of said bump is positioned on said substrate prior to securement of said first conductive line section to said substrate, and wherein the low melting-point conductor of said bump is positioned directly against said first conductive line section after securement thereto.

6. The device of claim 2 wherein the high melting-point conductor of said bump is positioned directly on said first conductive line section prior to securement of said first conductive line section to said substrate.

7. The device of claim 2 wherein the high melting-point conductor of said bump is positioned on said substrate prior to securement of said first conductive line section to said substrate, and wherein the low melting-point conductor of said bump is positioned directly against said first conductive line section after securement of said first conductive line section.

8. The device of claim 1 wherein said integrated passive device comprises a device chosen from the group consisting of an inductor, a coupler, a balun, and a transformer.

9. The device of claim 1 wherein said first conductive line section is manufactured of a material chosen from the group consisting of copper, silver, and gold.

10. The device of claim 1 wherein said carrier is manufactured of a material chosen from the group consisting of gallium arsenide, glass, silicon on insulator, laminate, silicon, a semiconductor material, and a high resistivity material.

11. The device of claim 1 wherein said substrate is manufactured of a material chosen from the group consisting of gallium arsenide, glass, silicon on insulator, laminate, silicon, a semiconductor material, and a high resistivity material.

12. The device of claim 1 wherein said first conductive line section comprises a section of a planar, spiral path.

13. The device of claim 1 wherein said first conductive line section comprises a section of a planar interconnect routing path.

14. The device of claim 1 wherein said first and second conductive line sections comprise sections of at least two planar paths, concentrically positioned adjacent one another.

15. The device of claim 1 wherein said first and second conductive line sections comprise sections of at least two planar meandering paths, positioned adjacent one another.

16. The device of claim 1 wherein said first conductive line section defines a path that includes at least one segment in a first plane and at least one segment in a second plane, and wherein a junction between said one segment in said first plane and said one segment in said second plane is defined by said bump.

17. The device of claim 1 wherein said device defines a Quality Factor of at least 20.

18. The device of claim 1 wherein said bump includes a pillar region manufactured of one of copper and silver, and a cap region manufactured of a material chosen from one of tin, a tin/silver alloy, and a tin/silver/copper alloy.

19. The device of claim 1 wherein said thickness T is at least 40 μ

m.

20. The device of claim 1 wherein said first conductive line section is manufactured on said carrier by a micro fabrication process including electroplating.

21. An integrated passive device, comprising:

a first conductive line section positioned on a planar outermost surface of a carrier and having a width W and a thickness T, where T/W is at least 0.75;

a second conductive line section positioned on said planar outermost surface of said carrier wherein a nearest distance from said first conductive line section to said second conductive line section is S, where S is at most 1.0.T;

a substrate; and

a bump positioned directly on said first conductive line section, said bump including a region of a high melting-point conductor and a region of a low melting-point conductor, said bump securing said first conductive line section to said substrate and having a height of at least 30 μ

m wherein said bump is positioned between said first conductive line section and said substrate.

22. The device of claim 21 wherein said thickness T is at least 40 μ

m.