Nonvolatile semiconductor memory device
First Claim
1. A nonvolatile semiconductor memory device comprising:
- a semiconductor substrate comprising a channel formation region formed between a pair of impurity regions;
a pair of field oxide films wherein the pair of impurity regions is between the pair of field oxide films;
a first insulating layer formed over the semiconductor substrate;
a floating gate formed over the first insulating layer and comprising at least a first layer and a second layer;
a second insulating layer formed over the floating gate; and
a control gate formed over the second insulating layer,wherein the first insulating layer, the floating gate, the second insulating layer and the control gate are overlapped with the channel formation region,wherein the first layer is in contact with the first insulating layer and includes a semiconductor material,wherein a band gap of the first layer is smaller than a band gap of the channel formation region in the semiconductor substrate, andwherein the first layer comprises an n-type impurity.
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Abstract
A nonvolatile semiconductor memory device which is superior in writing property and charge holding property, including a semiconductor substrate in which a channel formation region is formed between a pair of impurity regions, and a first insulating layer, a floating gate, a second insulating layer, and a control gate over the semiconductor substrate. The floating gate includes at least two layers. It is preferable that a band gap of a first layer included in the floating gate, which is in contact with the first insulating layer, be smaller than that of the semiconductor substrate. For example, it is preferable that the band gap of the semiconductor material for forming the floating gate be smaller than that of the channel formation region in the semiconductor substrate by 0.1 eV or more. This is because, by lowering the bottom energy level of a conduction band of the floating gate electrode than that of the channel formation region in the semiconductor substrate, a carrier injecting property and a charge holding property are improved.
96 Citations
67 Claims
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1. A nonvolatile semiconductor memory device comprising:
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a semiconductor substrate comprising a channel formation region formed between a pair of impurity regions; a pair of field oxide films wherein the pair of impurity regions is between the pair of field oxide films; a first insulating layer formed over the semiconductor substrate; a floating gate formed over the first insulating layer and comprising at least a first layer and a second layer; a second insulating layer formed over the floating gate; and a control gate formed over the second insulating layer, wherein the first insulating layer, the floating gate, the second insulating layer and the control gate are overlapped with the channel formation region, wherein the first layer is in contact with the first insulating layer and includes a semiconductor material, wherein a band gap of the first layer is smaller than a band gap of the channel formation region in the semiconductor substrate, and wherein the first layer comprises an n-type impurity. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 44, 52, 60)
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9. A nonvolatile semiconductor memory device comprising:
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a semiconductor substrate comprising a channel formation region formed between a pair of impurity regions; a pair of field oxide films wherein the pair of impurity regions is between the pair of field oxide films; a first insulating layer formed over the semiconductor substrate; a floating gate formed over the first insulating layer and comprising at least a first layer and a second layer; a second insulating layer formed over the floating gate; and a control gate formed over the second insulating layer, wherein the first insulating layer, the floating gate, the second insulating layer and the control gate are overlapped with the channel formation region, wherein the first layer is in contact with the first insulating layer, wherein the first layer has an electron affinity which is larger than an electron affinity of the channel formation region in the semiconductor substrate, and wherein the first layer comprises an n-type impurity. - View Dependent Claims (10, 11, 12, 13, 14, 15, 45, 53, 61)
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16. A nonvolatile semiconductor memory device comprising:
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a semiconductor substrate comprising a channel formation region formed between a pair of impurity regions; a pair of field oxide films wherein the pair of impurity regions is between the pair of field oxide films; a first insulating layer formed over the semiconductor substrate; a floating gate formed over the first insulating layer and comprising at least a first layer and a second layer; a second insulating layer formed over the floating gate; and a control gate formed over the second insulating layer, wherein the first insulating layer, the floating gate, the second insulating layer and the control gate are overlapped with the channel formation region, wherein barrier energy with respect to electrons in the first layer of the floating gate, formed by the first insulating layer, is higher than barrier energy with respect to electrons in the channel formation region in the semiconductor substrate, formed by the first insulating layer, and wherein the first layer comprises an n-type impurity. - View Dependent Claims (17, 18, 19, 20, 21, 22, 46, 54, 62)
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23. A nonvolatile semiconductor memory device comprising:
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a semiconductor substrate comprising a channel formation region formed between a pair of impurity regions; a pair of field oxide films wherein the pair of impurity regions is between the pair of field oxide films; a first insulating layer formed over the semiconductor substrate; a floating gate formed over the first insulating layer and comprising at least a first layer and a second layer; a second insulating layer formed over the floating gate; and a control gate formed over the second insulating layer, wherein the first insulating layer, the floating gate, the second insulating layer and the control gate are overlapped with the channel formation region, wherein the first layer is in contact with the first insulating layer, wherein the first layer comprises germanium and an n-type impurity. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32, 47, 55, 63)
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33. A semiconductor device comprising:
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an antenna; a memory circuit comprising; a semiconductor substrate comprising a channel formation region formed between a pair of impurity regions; a pair of field oxide films wherein the pair of impurity regions is between the pair of field oxide films; a first insulating layer formed over the semiconductor substrate; a floating gate formed over the first insulating layer and comprising at least a first layer and a second layer; a second insulating layer formed over the floating gate; and a control gate formed over the second insulating layer, wherein the antenna is operationally connected to the memory circuit, wherein the first insulating layer, the floating gate, the second insulating layer and the control gate are overlapped with the channel formation region, wherein the first layer is in contact with the first insulating layer and includes a semiconductor material, wherein a band gap of the first layer is smaller than a band gap of the channel formation region in the semiconductor substrate, and wherein the first layer comprises an n-type impurity. - View Dependent Claims (34, 48, 56, 64)
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35. A semiconductor device comprising:
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an antenna; a memory circuit comprising; a semiconductor substrate comprising a channel formation region formed between a pair of impurity regions; a pair of field oxide films wherein the pair of impurity regions is between the pair of field oxide films; a first insulating layer formed over the semiconductor substrate; a floating gate formed over the first insulating layer and comprising at least a first layer and a second layer; a second insulating layer formed over the floating gate; and a control gate formed over the second insulating layer, wherein the antenna is operationally connected to the memory circuit, wherein the first insulating layer, the floating gate, the second insulating layer and the control gate are overlapped with the channel formation region, wherein the first layer is in contact with the first insulating layer, wherein the first layer has an electron affinity which is larger than an electron affinity of the channel formation region in the semiconductor substrate, and wherein the first layer comprises an n-type impurity. - View Dependent Claims (36, 49, 57, 65)
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37. A semiconductor device comprising:
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an antenna; a memory circuit comprising; a semiconductor substrate comprising a channel formation region formed between a pair of impurity regions; a pair of field oxide films wherein the pair of impurity regions is between the pair of field oxide films; a first insulating layer formed over the semiconductor substrate; a floating gate formed over the first insulating layer and comprising at least a first layer and a second layer; a second insulating layer formed over the floating gate; and a control gate formed over the second insulating layer, wherein the antenna is operationally connected to the memory circuit, wherein the first insulating layer, the floating gate, the second insulating layer and the control gate are overlapped with the channel formation region, wherein barrier energy with respect to electrons in the first layer of the floating gate, formed by the first insulating layer, is higher than barrier energy with respect to electrons in the channel formation region in the semiconductor substrate, formed by the first insulating layer, and wherein the first layer comprises an n-type impurity. - View Dependent Claims (38, 50, 58, 66)
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39. A semiconductor device comprising:
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an antenna; a memory circuit comprising; a semiconductor substrate comprising a channel formation region formed between a pair of impurity regions; a pair of field oxide films wherein the pair of impurity regions is between the pair of field oxide films; a first insulating layer formed over the semiconductor substrate; a floating gate formed over the first insulating layer and comprising at least a first layer and a second layer; a second insulating layer formed over the floating gate; and a control gate formed over the second insulating layer, wherein the antenna is operationally connected to the memory circuit, wherein the first insulating layer, the floating gate, the second insulating layer and the control gate are overlapped with the channel formation region, wherein the first layer is in contact with the first insulating layer, wherein the first layer comprises germanium, and wherein the first layer comprises an n-type impurity. - View Dependent Claims (40, 41, 42, 43, 51, 59, 67)
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Specification