Semiconductor device and manufacturing method of the same

• US 8,212,312 B2
• Filed: 01/20/2012
• Issued: 07/03/2012
• Est. Priority Date: 01/28/2009
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Sasaki, Yuji
• Primary Examiner(s): Dang, Trung Q
• Application Number:
  US13/355,280
• Publication Number:
  US 20120112267A1
• Time in Patent Office: 165 Days
• Field of Search: 257/329, 257/339, 257/E29.262
• US Class Current: 257/329
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0684 characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
• CPC Class Codes: H01L 29/0688 characterised by the particular shape of a junction between semiconductor regions
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/32 the imperfections being within the semiconductor body
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

Disclosed herein is a semiconductor device including: a first conductivity type semiconductor base body; a first conductivity type pillar region; second conductivity type pillar regions; element and termination regions provided in the first and second conductivity type pillar regions, transistors being formed in the element region, and no transistors being formed in the termination region; body regions; a gate insulating film; gate electrodes; source regions; and body potential extraction regions, wherein voids are formed in the second conductivity type pillar regions of the termination region.

Claims

1. A semiconductor device, comprising:

a first semiconductor body;

a first region including a first semiconductor region covering a surface of the first semiconductor body;

a second region including a second semiconductor region;

element and termination regions provided in the first and second region,

a transistor formed in the element region, and wherein there is no transistor formed in the termination region;

a body region of the transistor in the element region formed at the surface of the first region and in contact with the second region, the body region including a second semiconductor region;

wherein

a void is formed in the second region of the termination region.

2. The semiconductor device of claim 1, wherein

a gate insulating film formed on the first region and the body region;

a gate electrode formed on the gate insulating film in such a manner as to straddle part of the body region and part of the surface of the first region;

a source region formed on part of the surface of the body region at end portions of the gate electrode, the source region including a first semiconductor region.

3. The semiconductor device of claim 1, wherein

a body potential extraction region is formed on the surface of the body region, the body potential extraction region including a second impurity diffusion layer.

4. The semiconductor device of claim 1, wherein

a second region including a second semiconductor region is arranged in the direction approximately parallel to a main surface of the first semiconductor body.

5. The semiconductor device of claim 4, wherein

a second region is arranged in a striped pattern in approximately the same direction as the first region.

6. The semiconductor device of claim 1, wherein

each second region in the termination region is shaped differently from the second region in the element region.

7. The semiconductor device of claim 6, wherein

the second region in the termination region is formed so as to gradually increase in thickness from where it contacts the second region toward the end portion of the semiconductor device.

8. The semiconductor device of claim 6, wherein

the second region in the termination region is formed so as to gradually decrease in thickness from where it contacts the second region toward the end portion of the semiconductor device.

9. The semiconductor device of claim 6, wherein

the end portions of the second region in the termination region are formed with a rectangular shape and wider than the second region in the element region.

10. The semiconductor device of claim 1, wherein

each second region in the termination region is separated from the second region in the element region.